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SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from,
or refreshed. Fast gives faster performance; and slow gives more
stable performance. This field applies only when synchronous
DRAM is installed in the system.
SDRAM RAS PrechargeTime
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. Fast gives
faster performance; and slow gives more stable performance.
This field applies only when synchronous DRAM is installed in
the system.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not
reset this field from the default value specified by the system
designer.
SDRAM Precharge Control
When enabled, all CPU cycles to SDRAM result in an All Banks
Precharge Command on the SDRAM interface.
DRAM Data Integrity Mode
Select Parity or ECC (error correcting code), according to the
type of installed DRAM.
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SBC-676 User Manual
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