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4. ADDRESSING
Xerox 530 and Sigma
2/3
addressing techniques enable the
central processor to compute an effective memory address
for Class 1 instructions d'uring their execution cycle. A thor-
ough un'de'rstanding of this process is necessary for usi ng Ex-
tended Symbol addreSSing features most effectively.
rhe address control bits (4 through 7) of the
instruction
word determin'e the type of addressing to be used and the
various address computation options.
The format of the in-
struction word is
The address computation process is as follows:
Step 1.
Determi ne Reference Address
Bit Positions
4
5
6
7
Effect
o
o
o
o
Reference address
=
Disp lacement
Reference address
==
Displacement +
va lue in index register
2
(a base ad-
dress). This is "base-relativeaddress-
ing" or "pre-indexing".
Reference address
=
Value in
H
register
(address of the instruction)
+
Displace-
ment. This is" self-re lative forward ad-
dressing" .
Reference address
=
Va lue in H register
(address of the instruction) - Displace-
ment.
This is "self-relative backward
addressing
fl
•
(The computer assumes
bifs
7
and 8-15 to bea 9-bit two's com-
plement negative integer which the
computer sign-extends to a 16-bit va lue
and adds to the 'Ialue in
H.)
Note: A
II
address ca leu lati ons are pet formed modu
102
16
Step
2.
Determine Direct Address
Bi t Posi ti ons
4 5
6
7
Efj:'~ct
o
Direct address
=
Reference address.
This is "direct addressing".
Direct address
=
Contents of the word
whose address is equa I to the reference
address. This is
II
indirect addressing".
Step
3.
Determine Effective Address
Bit Positions
4
5
6
7
Effect
o
Effective address
=
Direct address.
18
Addressing
Effective address
==
Direct address
+
va lue in index reg ister 1 (an index
value). This is "post-indexing".
The effective address for an instruction, therefore, is the
final 16-bit address value developed for the instruction"
starting with the displacement value given. The core mem-
ory locationwhose address equals the effective address is re-
ferred to as the" effecti
ve
location" and its contents are
the" effective word" .
Extended Symbol uses the entri es in the argument Held of the
symbo lie instruction statement, the execution location coun'-
ter, symbol tab Ie entries, and assemb Iy condi ti ons indi cated
by various assemb ler directi ves to assemble Class 1 i nstruc-
tions with the most efficient type of addressing possible.
The remainder of this chapter describes the automatic address-
ing techniques employed by Extended Symbol and various
kind'S of addressing control that can be applied by the pro-
grammer.
ARGUMENT ADDRESSING FORMAT
The pro-grammercan set the address control bits and displace-
ment of a Class 1 instruction using argument addressing en-
tries.
These entries have the form
*a,
'X,
b
where
*
a
x
b
OPTIONAL.
Indicates indirect addressing; sets
bit
5
=:
1.
REQUIRED.
An expression - multitermed, single
~ymbol,
constant, or literal - that represents the
argument address (bits 8-15).
The "a" must be
single-termed if it is a forward or external ref-
erence.
OPTIONAL.
An index tag specifying post-
indexing with index register 1; sets bit 6.
If x
I-
0,
post-indexing is specified.
If x :. : ::
0
or is blank, post-indexing is not
specified.
OPTIONAL.
A base tag specifying base-relative
addressing with index register 2; sets bit 7.
If b
I- 0,
base-relative addressing is specified.
and the argument address "a" is used by the assem-
bler to construct a displacement in the range
0
through +255 relative to a base address.
If b
=
0 or is blank, the assembler determines if
base-relative addressing will be generated for the
instruction.
(See "Base-Relative Address Control"
and "Automatic Addressing" in this chapter).
If the x tag is omitted but the b tag is present, two commas
must be placed between the argument address entry and the
base tag.
If b is omitted: the cornma following x may be
ami tted.
If ooth b and x are ami tted, the two commas are
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