Xerox 530 Language And Operations Reference Manual page 21

With the exception noled below, Class 1 instructions are
written in symbolic form according to the following syntax:
label m *5:,x,b
I.
The menmonic operation code (m) determines the value
of OP (bi ts
0-3L
2.
Either an asterisk precedi ng the argument address or
certain assembly conditions determine bit
5,
the in-
d i rec t address bi t.
3.
The x tag in the argument field determines bit
6,
the
post-indexing bit.
4.
A b tag in the argument field may determine bit
7,
which
is the pre-indexing or base-relative addressing bit. As
mentioned previously, the assembler may set bit 7 any-
way, depending on certain conditions. This is explained
in Chapter
4.
5.
The form and content of the argument address (a) de-
termine which instruction subclass is generated.
If
the
argument address is not within self-relative or non-
relative addressing range of the instruction, the b tag
is not I, and no BASE directive is encountered, the
following results:
a.
If
the address is indicated as indirect, the instruc-
tion is incompletely translated and tagged as an
error.
b. If the address is not designated as indirect, the
assembler develops an address literal and trans-
lates the instruction into an indirect reference
to the location of the literal.
An indirect address literal generated by Extended
Symbol is always placed in a literal pool within
self-relative addressing range of the instruction
that references the literal. By this process, ad-
dress va lues that otherwise would be out of range
for the instruction may be used; address values ob-
tained indirectly may specify any location within
the limits of available memory.
More complete information on Extended Symbol ad-
dressing is given in Chapter
4.
Single precision Class
1
instructions include basic, general
register, and floating-point instructions.
BASIC INSTRUCTIONS
Mnemonic Function
LDA Load Accumulator
STA Store Accumulator
ADD
Add
14 Xerox
530
and Sigma
2/3
Machint; Instructions
Mnemonic
Function
SUB
Subtract
MUL
Multiply
DIV
Divide
B Branch Unconditionally
1M Increment Memory
LDX Load Index
CP Compare
S Shift
RD Read Direct
WD Write Direct
AND Logical AND
GENERAL REGISTER INSTRUCTIONS
Mnemonic Function
LWt
Load
'Nord
ANDt
AND Word
AWt
Add Word
SW
t
Subtract Word
CW
t
Compare Word
STW
t
Store Word
Syntactically, these general register instructions differ from
the basic instructions in that they must specify a register:
~ *~,
x,b
l
where r is a register expression
(2~ r~
6). Since
AND is also part of the basic instruction set, it retains its
meaning as a Logical AND instruction when it is used with-
out the register expression.
These mnemonics generate two instructions. The first is the
Set General Register instruction which has the form
SGR gr
and wi" generate
where gr designates the register affected (2
~grS
6).
t
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530
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y.