HP E1563A User Manual page 135

Master-Slave
Operation
Trigger Mode
NORMal Mode
MASTer Mode
SLAVe Mode
Master-Slave Diagrams
Appendix B
The HP E1563A and HP E1564A Digitizers can be configured in a master-
slave configuration. This configuration allows a master module and one or
more slave modules to have their measurements synchronized.
Synchronization occurs by having all channels trigger off of the same trigger
event as well as all channels sampling from one sample signal.
•
The sample synchronization signal is always generated by the master.
•
The TTL trigger event can be generated by either the master module or
any of the slave modules. This allows a slave module (as well as the
master module) to use one of the four internal trigger sources or their
external trigger source to trigger a measurement.
Both the trigger signal and the sample signal are put on the VXI backplane
TTL trigger (TTLT) lines where the master module and all slave modules
receive the signals simultaneously. TTL trigger lines are used in pairs
between the master and slave(s) where one TTL trigger line carries the
sample signal and the other carries the trigger signal. The next section
describes how these TTL trigger lines are paired.
Bits 5 and 6 of the Trigger Source/Control register are used to configure
Digitizers for master-slave operation. The module functions as a normal
module when both bits are "0".
The default setting for trigger mode is normal (bits 5 and 6 of the Trigger
Source/Control register are both "0") which configures the module as an
individual instrument.
Bit 6 of the Trigger Source/Control register is used to configure a module as
a master. The eight TTL trigger lines (TTLT0-TTLT7) on the VXI
backplane allow four different pairings as shown in Table 2-1 (MASTer0-
SLAVe0, MASTer2-SLAVe2, MASTer4-SLAVe4 and MASTer6-
SLAVe6). You must select an unused set of TTL trigger lines for the
master-slave coupling when determining which master mode to set. Do not
use a TTLT line already used as a sample or trigger source.
Bit 5 of the Trigger Source/Control register is used to configure a module as
a slave to a MASTer0 module. MASTer0 and SLAVe0 modules share TTL
trigger lines TTLT0 and TTLT1. TTLT0 carries the sample signal and
TTLT1 carries the trigger signal. The following table shows all pairs of TTL
trigger lines for each master-slave mode.
Table 3-2. Master-Slave Modes.
MASTer MODE SLAVe MODE
MASTer0
MASTer2
MASTer4
MASTer6
Figure B-1 illustrates a module configured as a master module.
Figure B-2 illustrates a module configured as a slave module.
HP E1563A and E1564A Register-Based Programming 135
Sample line
SLAVe0 TTLT0
SLAVe2 TTLT2
SLAVe4 TTLT4
SLAVe6 TTLT6
Trigger line
TTLT1
TTLT3
TTLT5
TTLT7