NAD T737 Service Manual page 18

IC PIN DESCRIPTION (IC112: ADV7342: VIDEO ENCODER)
Pin No. Mnemonic
Y7 to Y0
13, 12,
9 to 4
29 to 25, C7 to C0
18 to 16
62 to 58, S7 to S0
55 to 53
52, 51, 15, TEST5 to
14, 3, 2 TEST0
30 CLKIN_A
63 CLKIN_B
50 S_HSYNC
49 S_VSYNC
22
P_HSYNC
23 P_VSYNC
24 P_BLANK
48 SFL/MISO
47 R
SET1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V 1
DD_IO
PIN 1
TEST0
2
TEST1
3
Y0
4
Y1 5
Y2
6
ADV7342/ADV7343
Y3
7
Y4
8
Y5
9
V
10
DD
DGND 11
Y6
12
Y7
13
TEST2
14
TEST3 15
C0
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Input/
Output Description
I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.
I 8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.
I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.
I Unused. These pins should be connected to DGND.
I Pixel Clock Input for HD Only (74.25 MHz), ED
I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
I/O SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
I
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
I ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
I ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
I/O Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
I This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from R
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from R
TOP VIEW
(Not to Scale)
1
to AGND.
SET1
2-5
48 SFL/MISO
R
47
SET1
V
46
REF
COMP1
45
44 DAC 1
DAC 2
43
DAC 3
42
V
41
AA
AGND
40
DAC 4
39
38 DAC 5
DAC 6
37
R
36
SET2
COMP2
35
34 PV
DD
EXT_LF1
33
Only (27 MHz or 54 MHz) or SD Only (27 MHz).
to
SET1