JHCTech FEBC-3150 User Manual page 38

Aluminum chassis , fan less design, intel core 4th gen i3/i5/i7 processor, 2xddr3l 1600 sodimm, max 16gb, 3xmini pcie support 3g/lte/wifi/bt/gps/can, dvi-i/hdmi/vga display, 4xcom/8bit dio/4xusb/audio, 4xintel i210-it power over ethernet, 1xmsata and 2x2.
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Debug Command Line
- O A16 05
- O A15 32
// 5 sec // 3A
Watchdog Timer Function
Watch dog timer is provided for system controlling. If time‐out can trigger one signal to
high/low level/pulse, the signal is depend on register setting.
The time unit has two ways from 1sec or 60sec. In pulse mode, there are four pulse
widths can be selected (1ms/25ms/125ms/5sec). Others, please refer the device register
description as below.
Watchdog Timer Configuration Register 1‐ base address +05h
Bit
Name
7
Reserved
6
WDTMOUT_STS
5
WD_EN
4
WD_PULSE
3
WD_UNIT
2
WD_HACTIVE
WD_PSWIDTH
1‐0
Watchdog Timer Configuration Register 2‐ base address +06h
Bit
Name
WD_TIME
7‐0
5 minutes
R/W
Default
R
0
Reserved
If watchdog timeout event occurs, this bit will be set to
R/W
0
1. Write a 1 to this bit will clear it to 0.
If this bit is set to 1,the counting of watchdog time is
R/W
0
enabled.
Select output mode (0:level,1:pulse)of RSTOUT# by
R/W
0
setting this bit.
Select time unit (0:1sec, 1:60sec) of watchdog timer by
R/W
0
setting this bit.
Select output polarity of RETOUT# (1:high active,
R/W
0
0:low active) by setting the bit.
Select output pulse width of RSTOUT#
R/W
0
0:1 ms 1:25 ms 2:125 ms 3:5 sec
Table 5.3
R/W
Default
R/W
0
Table 5.4
31
User's Manual
Description
Description
Time of watchdog timer

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