Wdt Setting - JHCTech FEBC-3150 User Manual

Aluminum chassis , fan less design, intel core 4th gen i3/i5/i7 processor, 2xddr3l 1600 sodimm, max 16gb, 3xmini pcie support 3g/lte/wifi/bt/gps/can, dvi-i/hdmi/vga display, 4xcom/8bit dio/4xusb/audio, 4xintel i210-it power over ethernet, 1xmsata and 2x2.
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I/O port: I/O port:
0xA35 (base address)
0xA36 (base address)
7
6
X
X
Debug Command Line
-O A35 F2
-I A36 // Check Bit 3 Status

5.2.2 WDT Setting

I/O port:
A10 (base address) + 05h and
06h
1 Watchdog Timer Control
Register
The Watchdog Timer Control Register controls the WDT working mode. Write the value to
the WDT Configuration Port. The following table describes the Control Register bit
definition:
7
6
0
0
for Control Register (Read 0xF2h bit 3)
for Control Data Value
5
4
X
X
Ignition
Status
0 = Ignition off
1 = Ignition on
Figure 5.2
5
4
3
1
1
Timer
Unit
0 = 1 sec
1 = 60 sec *
Figure 5.3
30
User's Manual
3
2
1
X
X
2
1
0
Select output
pulse width of
RSTOUT#
00 = 1 ms
01 = 25 ms
10 = 125 ms*
11 = 5 sec
0
X
0

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