Running A Pre-Compiled Design On The Mark 1 - ValentFX Mark 1 FPGA Starter Manual

17. U4 - Abracon Corporation - 50MHz Oscillator (ASDMB-50.000MHZ-LC-T)
18. Push Button PB0
19. Push Button PB1
20. Push Button PB2
21. Push Button PB3
22. P1C Arduino Uno Header
23. LEDs - LED0 through LED7
24. Switches - SW0 through SW4
25. U1 - Future Technology Devices International Ltd. - FTDI UART to USB (FT231XQ-R)
26. J1 Micro USB Connector 1
27. Power Regulation Circuitry
28. J7 - JTAG Header
29. LEDs DC17 and DC18 - power and configuration status
30. P28 Header - BeagleBone IO
31. P6 Header - Raspberry Pi IO
32. P29 Header – BeagleBone IO

3.1. Running a Pre-Compiled Design on the Mark 1

The Mark 1 ships with a great "LED counter" demo design that has already been
your hands dirty right away, you can run this program right out of the box! Otherwise, skip down to
get started making your own FPGA design.
One difficulty with FPGAs is that their program or "configuration" is stored in a
it also loses the program it was running. Some FPGAs can store their configuration in
program automatically on power up without any support circuitry. However, these devices are normally called
programmable logic devices
than FPGAs. Fundamentally both are
The Mark 1 has a support microcontroller by NPX Semiconductor on it. This IC is used to configure the FPGA after power up. Using
a microcontroller to assist in the configuration of the FPGA is one of the Mark 1's best features. With this topology, the user can
"drag and drop" a program onto the device. The device can then be rebooted by power cycling or pressing the PB5, Reset button.
Then, on system reset, the NPX microcontroller's
FPGA. In this way, the NPX microcontroller makes "configuring" the FPGA very easy for the end user. If this topology wasn't used,
the user would need to purchase and extra programmer device to configure the FGPA after power up. This might, for example be a
programmer connected to the board's JTAG header. This procedure is much more tedious and would need to be performed every time
the FPGA powers on.
Steps to set the Mark 1's boot configuration file using the Windows "drag and drop" method:
1. Using a micro USB to standard USB
header.
(or CPLDs). CPLDs differ in several other ways from FGPAs and are designed to do different things
programmable logic
firmware
cable, plug the Mark 1 into your
Figure 2 – Micro USB Connection on J11
compiled
"volatile
non-volatile
devices.
will load the program the user downloaded to it, onto the Spartain 6
Windows
for you. If you're interested in getting
Developing Your Own Design
memory." After the FPGA loses its power
memory in order to restore their
complex
based computer using the J11 mini USB
to
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