ValentFX Mark 1 FPGA Starter Manual page 10

To add a top level HDL file, right click the target chip in the Hierarchy view (denoted by the model, xc6slx9...) and choose New
Source. This will bring up a view that allows you to add a design file to your project. There are many different types of files you can
choose here but for this instruction we will have you load a new "Verilog Module." Give it a name and click Next.
On clicking next you are presented with a GUI that lets you define the module's input and outputs. It's convenient to think of Verilog
HDL modules as chips on a circuit board. Typically a chip has a number of pins that are either inputs or outputs. This GUI lets the
user specify names for the module's IO, then, when the Verilog HDL file is generated and added to the project it will contain
definitions for these IOs. Setup your Verilog module like the picture below. Note that you don't need to specify these IO points as
being "buses" or what their most or least significant bit is – all of these IO points are just one bit (or wire - depending on how you
view the world).
Figure 9 – An Empty Design in the Hierarchy View
Figure 10 – New Source Wizard
P a g e | 8