ValentFX Mark 1 FPGA Starter Manual page 11

Figure 11 – A Top-Level Verilog Module's IO Definition
In the Hierarchy view you will see a new Verilog source file called "Mark1Starter_TopLevel.v." ".v" is the file extension for Verilog
files. Double click it and its contents will be shown in the text editor on the pane to the right. Here is what you should see:
Figure 12 – An Auto Generated Verilog Module
You will notice that the Verilog syntax is highlighted. Things marked in green are comments, blue are Verilog language keywords
and the pink at the top used to denote the module's timing information for simulating the design (we're not going to touch on design
simulation).
At this point you have your top-level Verilog module defined and all you need to do is add logic to it. The module takes in two bits
and can output two bits. One could even think of these as wires coming in and going out of our module. We will use the
"OSC_FPGA" input bit to define a system clock signal. This signal will be used to turn over the logic on a specific time base.
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