ValentFX Mark 1 FPGA Starter Manual page 14

This is where the "Implementation Constrains File" comes in. These files have a .ucf file extension and describe the design's "user
constraints." Design constrains are a set of rules the compilation process needs to take into account when building the design's binary
output file. This ".bit" file is output by the compilation process and is the file that gets downloaded and run on the FPGA as described
in the section called Running a Pre-Compiled Design on the Mark
Some examples of types of things that can be constrained in an FPGA design are:
•
Timing constraints
•
Logical constraints
•
Physical constraints
•
Mapping and Routing constraints (or directives)
•
Physical pin assignment
User constraint files can vary dramatically in complexity and detail. The topic is very vast and discussing it in detail is outside the
scope of this document.
So there is a huge amount of information to know surrounding how to constrain designs, but fortunately for us, our design only needs
to constrain a handful of items to work properly (this design is so simple we're also not going to worry about enforcing any timing
constraints either). All that we need to do is to define what hardware pins our top-level Verilog HDL module's inputs and outputs link
up to. We also give some details about the design's clock input, OSC_FPGA.
Start by adding a constraints file to the project. Right click anywhere in the project Hierarchy view and choose New Source. This
time, select Implementation Constraints File, give it a name and choose Next:
A Summary window will appear. Click Finnish. Now in your project Hierarchy view you will see a new ".ucf" file. Double click it.
The Text Editor view on the right window pane will show your file is totally empty. Add the following code to it then we will discuss
what each piece means:
1.
Figure 16 – Add a new constraints file to the design
Figure 17 – Implementation constraints file
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