1
4.11 POWER SUPPLYBLOCK of MAIN and I/O ASSYS
A
12.0V ±10%
12V ±10%
V+12V
B
C
D
IC4702
Variable-REG
(V+9V_A)
PQ200WNA1ZPH
E
V+12V_A
I/O ASSY
F
38
1
2
SW REG CONTROLED BY RELAY
6.5V -7%, +10%
V+6_5V
IC4703
5V-REG
(V+5V_A)
NJM2846DL3_05
V+6_5V_A
IC5004
3.3V-REG
(V+3_3V_AD)
NJM2846DL3_33
V+6_5V_A
IC4803
3.3V-REG
(V+3_3V_A_VDEC)
NJM2846DL3_33
PWR_TCL_VDEC_3_3V
V+1_2V_D
IC4502
BD8606FV
DCDCconv
V+6_5V_DD
V+2_5V_D
V+9V A
9V±3%
V+9V A
RGB SW
AUDIO(PIONEER MODEL only)
PRO-141FD
2
3
V+5V_A
V+5V_A
5V±2%
RGB SW, SYNC SEPA
AUDIO DAC (PIONEER MODEL only)
V+5V_A_SW
RGB SW
V+3_3V_AD
3.3V±2%
V+3_3V_AD_D
ADC
V+3_3V_A_VDEC
5V±2%
V+3_3V_A_VDEC
VDEC
V+2_5V_D2
V+2_5V_D
Q4521
2.5V, +1.7%, -3%
2.6V±1.7%
FET-SW
(V+2_5V_D2)
RSS100N03
PWR_CTL_VDEC_3_3V
V+1_2V_D
1.2V±2.4%
V+1_2V_D2
1.2V±2.4%
V+1_2V_D2_ARIA
V+1_2V_D2_ARIA_PLL1,
V+1_2V_D2_ARIA_PLL2,
V+1_2V_D2_ARIA_PLL3
V+1_2V_D2_ARIA_PLL4,
V+3_3V_D
V+3_3V_D4
Q4501
3.3V±2.5%
FET-SW
3.3V±2.5%
(V+3_3VD4)
UPA1917TE
PWR_CTL_VDEC_3_3V
V+1_8V_AD
IC
IC5005
3.3V±2.5%
3V-REG
1.8V-REG
(V+3V_A)
(V+1_8V_AD)
0
NJM2846DL3_ 05
NJM2846DL3_18
0
0
V+5V_D
V+3_3V_D
V+3_3V_D_VDEC
Q4504
3.3V±2.5%
FET-SW
(V+3_3V_D_VDEC)
RTQ040P02
PWR_CTL_VDEC_3_3V
IC4804
1.8V-REG
(V+1_8V_D_VDEC)
NJM2846DL3_18
PWR_CTL_VDEC_1_8V
3
4
17V ±5%
No Use
V+2_5V_D2_ARIA
V+2_5V_D2_ARIA_DDR_A,
V+2_5V_D2_ARIA_DDR_B,
V+2_5V_D2_ARIA_DDR_C
V+3_3V_D4
V+3_3V_D4_ARIA
V+3_3V_D4_ARIA_ROM
V+3_3V_A_ADC
V+1_8V_A_PLL
V+1_8V_AD_A
V+1_8V_AD_D
V+3_3V_D_VDEC
VDEC
V+3_3V_D2_VDEC
V+3_3V_D2_VDEC_RAM
V+1_8V_D_VDEC
4