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2.10 Powering Down
Figure 13
and
Figure 14
output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the
R1 and R2 resistor divider network. In
to GND. The input voltage for these plots is 24 V and the load is 5 Ω.
V = 10 V / div
IN
EN = 2 V / div
V
= 2 V / div
OUT
V = 10 V / div
IN
EN = 2 V / div
V
= 2 V / div
OUT
SLVUB76 – July 2017
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show the start-up waveforms for the TPS54335AEVM-010. In
Figure
Time = 2 msec / div
Figure 13. TPS54335AEVM-010 Shut-down Relative to V
Time = 2 msec / div
Figure 14. TPS54335AEVM-010 Shut-down Relative to EN
Copyright © 2017, Texas Instruments Incorporated
14, the output is inhibited by using a jumper at JP1 to tie EN
TPS54335AEVM-010 3-A Regulator Evaluation Module
Test Setup and Results
Figure
13, the
IN
11
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