Board Layout; Tps54335Aevm-010 Top-Side Assembly - Texas Instruments TPS54335AEVM-010 User Manual

3-a regulator evaluation module
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Board Layout

3
Board Layout
This section provides a description of the TPS54335AEVM-010, board layout, and layer illustrations.
3.1
Layout
Figure 15
through
EVM is laid out in a manner typical of a user application. The top and bottom layers are 2-oz. copper.
The top layer contains the main power traces for V
connections for the remaining pins of the TPS54335A and a large area filled with ground. To facilitate the
placement of the main input bypass capacitor as close to the V
VPHASE is routed to the bottom layer immediately at the pin 3 connection. It is routed back to the top
layer at the L1 inductor and C4 BOOT capacitor. The bottom layer contains a ground plane plus a copper
fill area for VPHASE, an etch run to connect the upper resistor of the voltage set point divider to the
regulation point at the J2 output connector, and a trace to connect the upper resistor of the UVLO set
point divider network to V
planes with multiple vias placed around the board including four vias directly under the TPS54335A device
to provide a thermal path from the top-side ground area to the bottom-side and internal ground planes.
The input decoupling capacitors (C2, and C1) and bootstrap capacitor (C4) are all located as close to the
IC as possible. In addition, the voltage set-point resistor divider components are also kept close to the IC.
The BSR010 PCB is set up to accommodate both the TPS54335A and TPS54336A. For TPS54335A, the
RT resistor R3 is used, while for TPS54336A, C3 is used to set the adjustable slow-start time. For the
TPS54335A, an additional input bulk capacitor may be required, depending on the EVM connection to the
input supply.
12
TPS54335AEVM-010 3-A Regulator Evaluation Module
Figure 17
show the board layout for the TPS54335AEVM-010. The topside layer of the
. The top-side ground areas are connected to the bottom and internal ground
IN
Figure 15. TPS54335AEVM-010 Top-Side Assembly
Copyright © 2017, Texas Instruments Incorporated
, V
, and VPHASE. Also on the top layer are
IN
OUT
and GND pins as possible, the trace for
IN
www.ti.com
SLVUB76 – July 2017
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