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This evaluation kit is designed for engineering evaluation in a controlled
lab environment and should be handled by qualified personnel ONLY.
High voltage will be exposed on the board during the test and even brief
contact during operation may result in severe injury or death.
Never leave the board operating unattended. After it is de-energized,
always wait until all capacitors are discharged before touching the board.
This product contains parts that are susceptible to damage by electrostatic
discharge (ESD). Always follow ESD prevention procedures when
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Summary of Contents for Gan Systems GS66502B-EVBDB
- Page 1 Visit www.gansystems.com for the latest version of this user’s guide. This evaluation kit is designed for engineering evaluation in a controlled lab environment and should be handled by qualified personnel ONLY. High voltage will be exposed on the board during the test and even brief contact during operation may result in severe injury or death.
- Page 2 The GS665XXX-EVBDB daughter board style evaluation kit consists of two GaN Systems 650V GaN Enhancement-mode HEMTs (E-HEMTs) and all necessary circuits including half bridge gate drivers, isolated power supplies and optional heatsink to form a functional half bridge power stage. It allows users to easily evaluate the GaN E-HEMT performance in any half bridge-based topology, either with the universal mother board (P/N: GS665MB-EVB) or users’...
- Page 3 The 3 power pins are: VDC+: Input DC Bus voltage VSW: Switching node output VDC-: Input DC bus voltage ground return. Note that control ground 0V is isolated from VDC-. Iso. DC/DC ENABLE or Bootstrap PWMH VDC+ Si8271 Iso.
- Page 4 A. 2x GaN Systems 650V E-HEMT GS66508T(30A/50mΩ) or GS66516T (60A/25 mΩ). The PCB footprints are universal and compatible for both packages B. 5V-9V isolated DC/DC gate drive power supply C. Decoupling capacitors C4-C11 D. Isolated gate driver Silab Si8271 E. Optional current shunt position JP1.
- Page 5 Bipolar gate drive bias with +6V and -3V for turning off is chosen for this design for more robust gate drive and better noise immunity. 5V-9V isolated DC/DC converters are used for gate drive. 9V is then splited into +6V and -3V bias by using 6V Zener diode ...
- Page 6 The board provides an optional current shunt position JP1 between the source of Q2 and power ground return. This allows drain current measurement for switching characterization test such as Eon/Eoff measurement. The JP1 footprint is compatible with T&M Research SDN series coaxial current shunt (recommended P/N: SDN-414-10, 2GHz B/W, 0.1Ω) ...
- Page 7 BNC case To oscilloscope probe input (use 50Ω termination) BNC tip 1. GS66508T or GS66516T has a thermal pad at the top side for improved heat dissipation. Instead of relying on PCB for cooling, the heat can be transferred to heatsink directly from the top reducing the total thermal resistnace.
- Page 8 ° 5. The TIM we use on this assembly is Berguist SilPad 1500ST, the measured total thermal ® resistance can be found in Figure 9. Compared to bottom cooled design, T package eliminates the PCB thermal resistance and significantly improve the thermal performance. Theraml grease is typically not needed on the assembly.
- Page 9 M3 Screw Lock Washter Insulated bushing FR4 PCB GaNPX T GaNPX T Heatsink...
- Page 10 Optional Cout time circuit GaN Systems provides a universal 650V mother board (ordering part number: GS665MB-EVB, sold separately) that can be used as the basic evaluation platform for all the daughter boards. The universal 650V mother board evaluation kit includes following items: 1.
- Page 11 0.1uF 112538 D1 PMEG2005EB 49R9 SOD523 100R D2 PMEG2005EB 49R9 100R 74VHC132 R1206 R1206 74VHC132 1K00 OUTPUT SOD523 100pF 1K00 100pF 49R9 INVERTED 74VHC132 74VHC132 PWM OUTPUT The top and bottom switches PWM inputs can be individually controlled by two jumpers J4 and J6. Users can choose between a pair of complementary on-board internal PWM signals (non-inverted and inverted, controlled by J7 input) with dead time or external high/low side drive signals from J5 (users’...
- Page 12 Test points are designed in groups/pairs to facilitate probing: Test points Name Description TP1/TP2 +5V/0V 5V bias power TP7/TP8 PWMIN/0V PWM input signal from J7 TP4/TP3/TP13 PWMH/PWML/0V High/low side gate signals to daughter board TP9/TP10 VDC+/VDC- DC bus voltage TP11/TP12 VOUT/VDC- Output voltage TP6/TP5...
- Page 13 CON3 VDC+ INPUT (J7) CON2 400V DC CON4 CON5 CON1 CON6 CON7 VDC- t1 t2 t3 Double pulse test allows easy evaluation of device switching performance at high voltage/current without the need of actually running at high power. It can also be used for switching loss (Eon/Eoff) measurement and other switching characterization parameter test.
- Page 14 This is standard half bridge configuration that can be used in CON3 VDC+ following circuits : CON2 Synchronous Buck DC/DC Single phase half bridge inverter CON5 ZVS half bridge LLC 400V DC CON4 Phase leg for full bridge DC/DC or CON1 ...
- Page 15 The daughter board allows users to easily evaluate the GaN performance in their own systems. Refer to the footprint drawing of GS665XXX-EVBDB as shown below: 1 3 5 2 4 6 1. All units are in mm. 2. Pin 1-6: Dia. 1mm 3.
- Page 16 Follow the instructions below to quickly get started with your evaluation of GaN E-HEMT. Equipment and components you will need: Four-channel oscilloscope with 500MHz bandwidth or higher high bandwidth (500MHz or higher) passive probe high bandwidth (500MHz) high voltage probe (>600V) ...
- Page 18 Figure 17 shows the hard switching on waveforms at 400V/30A. A Vds dip can be seen due to the rising drain current (di/dt in the power loop ΔV=Lpxdi/dt, where Lp is the total power loop inductance). After the drain current reaches the inductor current, the Vds starts to fall. The Vgs undershoot spike is caused by the miller feedback via Cgd under negative dv/dt.
- Page 19 A T&M search coaxial current shunt (SDN-414-10, 0.1Ω) is installed for switching loss measurement as shown below.
- Page 20 The switching energy can be calculated from the measured switching waveform Psw = Vds*Id. The integral of the Psw during switching period is the measured switching loss. The channel deskewing is critical for measurement accurary. It is recommended to manually deskew Id against Vds as shown in Figure 21.
- Page 21 ° The switching loss measurements with drain current from 0 to 30A for GS66508T or up to 60A for GS66516T can be found in Figure 23. The turn-on loss dominates the overall hard switching loss. Eon at 0A is the Qoss loss caused by the Coss at high side switch. °C)
- Page 22 °C) The board is converted to a synchronous buck DC/DC converter and demonstrates efficiency close to 99% at 2kW. With forced air cooling, the board is tested up to 2kW for GS66508T with device temperature Tjmax = 75 °C and 2.4kW for GS66516T with Tjmax <70°C.
- Page 26 Top Layer Mid Layer 1 Mid Layer 2 Bottom Layer...
- Page 27 Bill of Materials...
- Page 29 Assembly Top Assembly Bottom...
- Page 31 The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies GaN Systems from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.
- Page 33 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: GaN Systems GS66516T-EVBDB...
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