400-Mhz Front Side Bus; Netburst Microarchitecture - HP ProLiant DL560 Technology Brief

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transistors into the circuit. Feature size is a major limiting factor in processing speed: As the feature

size decreases, the processing speed increases and the power requirements decrease. The

0.13-micron Xeon processor has a smaller feature size and faster circuitry than 0.18-micron Intel

processors.

HP manufactures the DL560 microprocessor/heatsink assembly as a single piece. It includes an

alignment mechanism to prevent damage to the processor during installation and pin protection to

prevent damage when the processor is placed on a flat surface.

400-MHz front side bus

All data transfers go to and from the processor over the front side bus (FSB). The Intel Xeon processor

MP has a 64-bit, quad-pumped bus running at 100 MHz. A normal (single-pumped) bus sends, or

latches, data out once per clock cycle on the rising or falling edge of the bus clock signal. A quad-

pumped bus latches data at four times the rate of a normal bus (Figure 5). This faster rate is achieved

by means of four overlapping clock strobes, each operating 90 degrees out of phase with the next.

Data is transmitted on the rising edge of each of the four strobes, four times per clock cycle. This

makes it possible to transfer 3.2 GB/s of data on a 100-MHz FSB, which is triple the data rate of the

Pentium III FSB (1.06 GB/s with a 133-MHz FSB).

Figure 5. Comparison of clock signals for a quad-pumped and a single pumped 100-MHz front side bus

Note: Only the data is quad pumped on these buses. The address bus for the processor is double pumped.

The Intel Xeon processor MP features Intel NetBurst microarchitecture. The NetBurst microarchitecture

supports MP speeds of up to 2.80 GHz and doubles the pipeline depth in the processor to enable

400-MHz core frequency. NetBurst microarchitecture also adds a Rapid Execution Engine and

Advanced Dynamic Execution. The Rapid Execution Engine allows the two integer Arithmetic Logic

Units (ALUs) in the processor to run at twice the core frequency, which increases performance by

allowing many integer instructions to execute in one half of the internal core clock period. Advanced

Dynamic Execution improves speculative execution and branch prediction internal to the processor.

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