Pioneer PDP-434CMX Service Manual page 183

5
Pin Function
Output Pins
Pin Name No.
37-30,
QE23 - QE0 27-20,
17-10
77,
75-69,
QO23 - QO0
66-59,
56-49
ODCK 44
DE 46
HSYNC 48
VSYNC 47
CTL1 40
CTL2 41
CTL3 42
Differential Signal Data Pins
Pin Name No.
RX0+ 90
RX0- 91
RX1+ 85
RX1- 86
RX2+ 80
RX2- 81
RXC+ 93
RXC- 94
EXT_RES 96
5
6
Type
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode and to
the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Out Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the input
data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock mode.
During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Out Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
Out PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pulldown
device brings the output to ground.
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
Out
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is not powered down by PDO#.
Out General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Type
Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
Impedance Matching Control. An external 390Ω resistor must be connected between AVCC
Analog
and this pin.
PDP-504CMX/1
6
7
Function
Function
7
8
A
B
C
D
E
F
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