Pcie Slot Breakdown (Kaby Lake-X) - EVGA X299 DARK Owner's Manual

EVGA X299 DARK (151-SX-E299)

PCIe Slot Breakdown (Kaby Lake-X)

PCIe Lane Distribution (Core
77xx, 16 Lane Processors)
PE1 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE2)

o PE1 can be disabled completely to run two M.2 drives
PE2 – x16 (Gen3, x8 lanes from CPU, shares 8 of PE1's 16 lanes)

o PE2 will be the only GPU ready slot when running two M.2 drives.
PE3 – x16 (Not functional on 16 lane processors)

PE4 – x16 (Not functional on 16 lane processors)

PE5 – x4 (Gen3, x4 lanes from PCH)

PE6 – x16 (Gen3, x4 lanes from PCH)

o Must be enabled in BIOS, which disables 80mm M.2/Optane
port
 Use of SLI DISABLES U.2 slots and M.2 Key-M(PM1)
slots
™
i5-76xx and i7-
PM2
™
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