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SERR signal condition
• [None] - Disables assertion of SERR# on memory error
• [Single bit] - Enables SERR# assertion on single-bit memory errors
• [Multiple bit] - Enables SERR# assertion on multi-bit memory errors
• [Both] - Enables SERR# assertion on both single and multi-bit memory errors
Memory Branch Mode
[Interleave] - This function can write data interleaved between multiple of memories. It
can increase the speed of memory writing.
[Mirror] - This function can write duplicate data onto a pair of memories. If one of the
mirrored memories suffers a failure or does not respond, the remaining memory will
continue to function.
Branch 0/1 Rank Sparing
System will keep a part of branch free. If the other part suffers a failure, the keeping
part will pinch-hit and continue to function.
Advanced Chipset Control
Press <Enter> to enter the sub-menu and the following screen appears:
POST Errors
This item can pause boot when POST errors occur. If you disable it, the system will
always attempt to boot.
Figure 52: Advanced Chipset Control Menu
Vig395P Motherboard Manual
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