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Mitsubishi Electric MELSEC iQ-R C Programming Manual page 38

Melsec iq-r series programmable controller
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Device
Link direct device (Link input)
Link direct device (Link output)
Link direct device (Link relay)
Link direct device (Link register)
Link direct device (Link special relay)
Link direct device (Link special register)
Intelligent function module device, module access device
CPU shared memory, CPU buffer memory (CPU No.1 area)
CPU shared memory, CPU buffer memory (CPU No.2 area)
CPU shared memory, CPU buffer memory (CPU No.3 area)
CPU shared memory, CPU buffer memory (CPU No.4 area)
Fixed cycle communication area (CPU No.1 area)
Fixed cycle communication area (CPU No.2 area)
Fixed cycle communication area (CPU No.3 area)
Fixed cycle communication area (CPU No.4 area)
Global label
Safety input
Safety output
Safety internal relay
Safety link relay
Safety timer
Safety retentive timer
Safety counter
Safety data register
Safety link register
Safety special relay
Safety special register
*1 The following CPUs are accessible:
Q12DCCPU-V with a serial number of which first 5 digits are "12042" or later
Q24DHCCPU-V, Q24DHCCPU-LS, Q24DHCCPU-VG, and Q26DHCCPU-LS
*2 Q00JCPU is not accessible.
*3 The following CPUs are accessible:
Q12DCCPU-V (Extended mode),
Q24DHCCPU-V, Q24DHCCPU-LS, Q24DHCCPU-VG, and Q26DHCCPU-LS
1 COMMON ITEMS
36
1.3 MELSEC Data Link Functions
Access
method
Jn\X
Batch/random
Jn\Y
Batch/random
Jn\B
Batch/random
Jn\W
Batch/random
Jn\SB
Batch/random
Jn\SW
Batch/random
Un\G
Batch/random
Batch
Random
Batch
Random
Batch
Random
Batch
Random
Batch
Random
Batch
Random
Batch
Random
Batch
Random
GV
Batch
Random
SA\X
Batch/random
SA\Y
Batch/random
SA\M
Batch/random
SA\B
Batch/random
SA\T
Batch/random
SA\ST
Batch/random
SA\C
Batch/random
SA\D
Batch/random
SA\W
Batch/random
SA\SM
Batch/random
SA\SD
Batch/random
Access target CPU
(1)
(2)
(3)
(4)
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
(5)
(6)

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