Mitsubishi Electric MELSEC iQ-R C Programming Manual page 16

Melsec iq-r series programmable controller
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• Accessing the other CPU
The following table shows the accessible devices when accessing the other CPUs (that is a CPU module and a C Controller
module in a multiple CPU system).
No.
Access target CPU
(1)
RCPU
(2)
R12CCPU-V
: Accessible, : Not accessible
Device
Input relay
Output relay
Latch relay
Internal relay
Special relay
Annunciator
Timer (Contact)
Long timer (Contact)
Timer (Coil)
Long timer (Coil)
Counter (Contact)
Long counter (Contact)
Counter (Coil)
Long counter (Coil)
Timer (Current value)
Long timer (Current value)
Counter (Current value)
Long counter (Current value)
Data register
Special register
Index register
Long index register
File register
Refresh data register
Link relay
Link register
Link special relay
Retentive timer (Contact)
Long retentive timer (Contact)
Retentive timer (Coil)
Long retentive timer (Coil)
Link special register
Edge relay
Own station random access buffer
Retentive timer (Current value)
Long retentive timer (Current value)
Remote register for sending
Remote register for receiving
Own station buffer memory
Link direct device (Link input)
Link direct device (Link output)
Link direct device (Link relay)
Link direct device (Link register)
1 COMMON ITEMS
14
1.3 MELSEC Data Link Functions
Access method
X
Batch/random
Y
Batch/random
L
Batch/random
M
Batch/random
SM
Batch/random
F
Batch/random
T
Batch/random
LT
Batch/random
T
Batch/random
LT
Batch/random
C
Batch/random
LC
Batch/random
C
Batch/random
LC
Batch/random
T
Batch/random
LT
Batch/random
C
Batch/random
LC
Batch/random
D
Batch/random
SD
Batch/random
Z
Batch/random
LZ
Batch/random
R
Batch/random
ZR
Batch/random
RD
Batch/random
B
Batch/random
W
Batch/random
SB
Batch/random
ST
Batch/random
LST
Batch/random
ST
Batch/random
LST
Batch/random
SW
Batch/random
V
Batch/random
Batch/random
ST
Batch/random
LST
Batch/random
RWw
Batch/random
RWr
Batch/random
Batch/random
Jn\X
Batch/random
Jn\Y
Batch/random
Jn\B
Batch/random
Jn\W
Batch/random
Access target CPU
(1)
(2)

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