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MSP430FG4619, MSP430FG4618, MSP430FG4617, MSP430FG4616
MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616
SLAS508J – APRIL 2006 – REVISED JUNE 2015
6.9.2 Oscillator and System Clock
The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which
includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO),
and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of
both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the watch crystal frequency. The internal DCO provides a fast turnon clock source and
stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
•
Main clock (MCLK), the system clock used by the CPU
•
Submain clock (SMCLK), the subsystem clock used by the peripheral modules
•
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
6.9.3 Brownout, Supply Voltage Supervisor (SVS)
The brownout circuit provides the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable level and supports both
supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is
not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V
not have ramped to V
changed until V
CC
reaches V
.
CC(min)
6.9.4 Digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
•
All individual I/O bits are independently programmable.
•
Any combination of input, output, and interrupt conditions is possible.
•
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
•
Read and write access to port-control registers is supported by all instructions
•
Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB, respectively.
6.9.5 Basic Timer1 and Real-Time Clock
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter.
Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-
time clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap-
year correction.
6.9.6 LCD_A Drive With Regulated Charge Pump
The LCD_A driver generates the segment and common signals required to drive a segment LCD display.
The LCD_A controller has dedicated data memory to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are
supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage
with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and,
thus, contrast by software.
6.9.7 Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software
problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function
is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
56
Detailed Description
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at that time. The user must make sure the default FLL+ settings are not
CC(min)
reaches V
. If desired, the SVS circuit can be used to determine when V
CC(min)
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