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1 Device Overview
1.1
Features
1
• Low Supply Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
– Standby Mode (LPM3):
Watchdog With Crystal and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
– Shutdown Real-Time Clock (RTC) Mode
(LPM3.5):
Shutdown Mode, Active RTC With Crystal:
1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.3 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
20-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 32 MHz (XT2)
1.2
Applications
Analog and Digital Sensor Systems
Digital Motor Control
Remote Controls
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635
MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630
MSP430F563x Mixed-Signal Microcontrollers
Tools &
Technical
Software
Documents
SLAS650E – JUNE 2010 – REVISED DECEMBER 2015
• Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
• Two Universal Serial Communication Interfaces
(USCIs)
– USCI_A0 and USCI_A1 Each Support:
Enhanced UART Supports Automatic Baud-
Rate Detection
IrDA Encoder and Decoder
Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
2
I
C
Synchronous SPI
• Full-Speed Universal Serial Bus (USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB Power System
– Integrated USB-PLL
– Eight Input and Eight Output Endpoints
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Shared Reference, Sample-and-Hold, and
Autoscan Feature
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• Voltage Comparator
• Hardware Multiplier Supports 32-Bit Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Six-Channel Internal DMA
• RTC Module With Supply Voltage Backup Switch
Table 3-1
Summarizes the Available Family
Members
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
Thermostats
Digital Timers
Hand-Held Meters
Support &
Community

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Summary of Contents for Texas Instruments MSP430F563x

  • Page 1 Documents MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635 MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630 SLAS650E – JUNE 2010 – REVISED DECEMBER 2015 MSP430F563x Mixed-Signal Microcontrollers 1 Device Overview Features • Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7 Capture/Compare Registers •...
  • Page 2: Device Overview

    The digitally controlled oscillator (DCO) allows the device to wake up from low- power modes to active mode in 3 µs (typical). The MSP430F563x devices are microcontrollers with a high-performance 12-bit ADC, a comparator, two USCIs, USB 2.0, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.
  • Page 3 (12 ext/4 int) Port PJ Registers System Autoscan Figure 1-2. Functional Block Diagram – MSP430F5635, MSP430F5634, MSP430F5633 Device Overview Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 4 2.5V Registers Registers Backup Port PJ Registers System Figure 1-3. Functional Block Diagram – MSP430F5632, MSP430F5631, MSP430F5630 Device Overview Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 5: Table Of Contents

    5.25 PMM, SVM Low Side Documentation Support ........5.26 Wake-up Times From Low-Power Modes and Related Links ..........Reset Table of Contents Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 6: Functional Block Diagrams

    Trademarks, and Electrostatic Discharge Caution sections to it ............. • Added Section 8, Mechanical, Packaging, and Orderable Information Revision History Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 7: Device Comparison

    For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Device Comparison Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 8: Terminal Configuration And Functions

    P4.1/TB0.1 NOTE: DNC = Do not connect Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F5638, MSP430F5637, MSP430F5636 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 9: Pin Designation - Msp430F5635Ipz, Msp430F5634Ipz, Msp430F5633Ipz

    P4.1/TB0.1 NOTE: DNC = Do not connect Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F5635, MSP430F5634, MSP430F5633 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 10: Pin Designation - Msp430F5632Ipz, Msp430F5631Ipz, Msp430F5630Ipz

    P4.1/TB0.1 NOTE: DNC = Do not connect Figure 4-3. 100-Pin PZ Package (Top View) – MSP430F5632, MSP430F5631, MSP430F5630 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 11: Msp430F5631Izqw, Msp430F5630Izqw

    Table 4-1 Figure 4-4. 113-Pin ZQW Package (Top View) – MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635, MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 12: Signal Descriptions

    Analog power supply (1) I = input, O = output, N/A = not available on this package offering Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 13 (2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C VCORE Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 14 General-purpose digital I/O with port interrupt P4.6/TB0.6 Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 15 USB LDO output USB regulated power (internal use only, no external current loading) AVSS3 Analog ground supply Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 16 Analog input A3 – ADC (not available on F5632, F5631, and F5630 devices) (3) When this pin is configured as reset, the internal pullup resistor is enabled by default. Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 17 Table 4-1. Signal Descriptions (continued) TERMINAL DESCRIPTION NAME Reserved Reserved. TI recommends connecting to ground (DVSS, AVSS). Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 18: Specifications

    (3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation. (4) A capacitor tolerance of ±20% or better is required. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 19 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-1. Frequency vs Supply Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 20: Active Mode Supply Current Into

    = 32768 Hz, f = 0 MHz ACLK MCLK SMCLK USB disabled (VUSBEN = 0, SLDOEN = 0). Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 21: Thermal Resistance Characteristics

    (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 22: Schmitt-Trigger Inputs - General-Purpose I/O

    , for all outputs combined should not exceed ±100 mA to hold the maximum voltage (OHmax) (OLmax) drop specified. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 23: Outputs - General-Purpose I/O (Reduced Drive Strength)

    (3) The output voltage reaches at least 10% and 90% V at the specified toggle frequency. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 24: Typical Characteristics - Outputs, Reduced Drive Strength (Pxds.y = 0)

    Figure 5-5. Typical High-Level Output Current vs High-Level Figure 5-4. Typical High-Level Output Current vs High-Level Output Voltage Output Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 25: Typical Characteristics - Outputs, Full Drive Strength (Pxds.y = 1)

    Figure 5-8. Typical High-Level Output Current vs High-Level Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage Output Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 26: Crystal Oscillator, Xt1, Low-Frequency Mode

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 27: Crystal Oscillator, Xt2

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 28: Internal Very-Low-Power Low-Frequency Oscillator (Vlo)

    (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 29: Dco Frequency

    Typical DCO Frequency, V = 3.0 V, T = 25°C DCOx = 31 DCOx = 0 DCORSEL Figure 5-10. Typical DCO frequency Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 30: Pmm, Brownout Reset (Bor)

    ≤ 3.6 V, 0 µA ≤ I(V ) ≤ 30 µA 1.44 CORE0 CORE mode, PMMCOREV = 0 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 31: Pmm, Svs High Side

    VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 32: Pmm, Svs Low Side

    LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (3) This value represents the time from the wake-up event to the reset vector execution. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 33: Timer_A, Timers Ta0, Ta1, And Ta2

    CHVx = 2 2.65 CHVx CHCx = 1 Charge limiting resistor CHCx = 2 kΩ CHARGE CHCx = 3 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 34 SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5- Figure 5-12. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 35 CKPL = 1 LO/HI LO/HI HD,MI SU,MI SOMI HD,MO VALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 1 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 36 (3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 Figure 5-14. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 37 LO/HI LO/HI HD,SI SU,SI SIMO HD,MO STE,ACC STE,DIS VALID,SO SOMI Figure 5-14. SPI Slave Mode, CKPH = 1 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 38 Pulse duration of spikes suppressed by input filter HD,STA SU,STA HD,STA HIGH SU,DAT SU,STO HD,DAT Figure 5-15. I C Mode Timing Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 39 ) × C + 800 ns, where n = ADC resolution = 12, R = external source resistance Sample Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 40 (4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 41 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature (°C) Figure 5-16. Typical Temperature Sensor Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 42 (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 43 ±0.5 LSB. The settling time depends on the external REFON capacitive load when REFOUT = 1. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 44 (2) This parameter is not production tested. (3) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 45 Gain Error = 100 pF Load Positive Negative DAC Code Figure 5-17. Linearity Test Load Conditions and Gain/Offset Definition Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 46 Load Load DAC12 = 100 pF O/P(DAC12_x) Load AV – 0.3 V Figure 5-18. DAC12_x Output Resistance Tests Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 47 Load ±1/2 LSB = 100 pF Load O/P(DAC12.x) settleLH settleHL Figure 5-19. Settling Time and Glitch Energy Testing Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 48 Load REF+ DAC12_yOUT Load Load DAC12_xOUT DAC12_1 DAC1 Toggle = 100 pF Load Figure 5-22. Crosstalk Test Conditions Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 49 (n + 1) (n + 1.5) CB_REF given tap n = 0 to 31 / 32 / 32 / 32 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 50 (5) This value, in series with an external resistor between PUR and D+, produces the R as outlined in the USB specification. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 51 TEST CONDITIONS UNIT Operating supply current PLL frequency PLL reference frequency PLL lock time LOCK PLL jitter 1000 Jitter Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 52 SBWTCK clock edge. (2) f may be restricted to meet the timing requirements of the module selected. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 53 6 Detailed Description Overview The MSP430F563x devices include a high-performance 12-bit ADC, a comparator, two USCIs, USB 2.0, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins. The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
  • Page 54 R10 + 2 → R10 Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source, D = destination Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 55 – Internal regulator disabled – No data retention – Wake-up signal from RST/NMI, P1, P2, P3, and P4 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 56 The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence (see Table 6-3). Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations SYSTEM WORD INTERRUPT SOURCE...
  • Page 57 MSP430F5638, MSP430F5637, MSP430F5636, MSP430F5635 MSP430F5634, MSP430F5633, MSP430F5632, MSP430F5631, MSP430F5630 www.ti.com SLAS650E – JUNE 2010 – REVISED DECEMBER 2015 Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F563x Configurations (continued) SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY INTERRUPT ADDRESS 0FFC8h Reserved Reserved ⋮...
  • Page 58 Entry sequence signal TEST/SBWTCK Entry sequence signal P1.1 Data transmit P1.2 Data receive Power supply Ground supply Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 59 Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A can be locked separately. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 60 The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented. There are 8 bytes of backup RAM available on MSP430F563x. It can be wordwise accessed by the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
  • Page 61 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) P2.6/P2MAP6 PM_NONE DVSS P2.7/P2MAP7 PM_NONE DVSS Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 62 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 63 No interrupt pending SYSBERRIV, Bus Error USB wait state time-out 0198h Highest Reserved 04h to 1Eh Lowest Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 64 (2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. (3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 65 The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I The MSP430F563x series includes two complete USCI modules (n = 0 to 1). 6.12.11 Timer TA0...
  • Page 66 TA1.2 CCI2A 45-P3.3 L8-P3.3 ACLK CCI2B (internal) CCR2 TA1.2 (1) Only on devices with peripheral module DAC12_A. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 67 L9-P3.6 CBOUT CCI1B (internal) CCR1 TA2.1 49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7 ACLK CCI2B (internal) CCR2 TA2.2 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 68 (1) Timer functions selectable by the port mapping controller. (2) Only on devices with peripheral module ADC12_A. (3) Only on devices with peripheral module DAC12_A. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 69 Up to 10 hardware triggers can be combined to form complex triggers or breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 70 (1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 71 UCSCTL4 UCS control 5 UCSCTL5 UCS control 6 UCSCTL6 UCS control 7 UCSCTL7 UCS control 8 UCSCTL8 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 72 Port P2 input P2IN Port P2 output P2OUT Port P2 direction P2DIR Port P2 pullup/pulldown enable P2REN Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 73 Port P6 direction P6DIR Port P6 pullup/pulldown enable P6REN Port P6 drive strength P6DS Port P6 selection P6SEL Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 74 Capture/compare 2 TA0CCR2 Capture/compare 3 TA0CCR3 Capture/compare 4 TA0CCR4 TA0 expansion 0 TA0EX0 TA0 interrupt vector TA0IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 75 Capture/compare 0 TA2CCR0 Capture/compare 1 TA2CCR1 Capture/compare 2 TA2CCR2 TA2 expansion 0 TA2EX0 TA2 interrupt vector TA2IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 76 32-bit operand 1 – signed multiply low word MPYS32L 32-bit operand 1 – signed multiply high word MPYS32H Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 77 DMA channel 3 destination address high DMA3DAH DMA channel 3 transfer size DMA3SZ DMA channel 4 control DMA4CTL Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 78 USCI I2C slave address UCB0I2CSA USCI interrupt enable UCB0IE USCI interrupt flags UCB0IFG USCI interrupt vector word UCB0IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 79 ADC memory control 5 ADC12MCTL5 ADC memory control 6 ADC12MCTL6 ADC memory control 7 ADC12MCTL7 ADC memory control 8 ADC12MCTL8 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 80 CBCTL1 Comp_B control 2 CBCTL2 Comp_B control 3 CBCTL3 Comp_B interrupt CBINT Comp_B interrupt vector word CBIV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 81 USB frame number USBFN USB control USBCTL USB interrupt enables USBIE USB interrupt flags USBIFG Function address USBFUNADR Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 82 Module X IN P1IE.x P1IRQ.x P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Figure 6-2. Port P1 (P1.0 to P1.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 83 Timer TA0.1 output P1.7/TA0.2 7 P1.7 (I/O) I: 0; O: 1 Timer TA0.CCI2B capture input Timer TA0.2 output Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 84 To Port Mapping P2IE.x P2IRQ.x P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Figure 6-3. Port P2 (P2.0 to P2.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 85 7 P2.7 (I/O) I: 0; O: 1 Mapped secondary digital function ≤ 19 (1) X = Don't care Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 86 Module X IN P3IE.x P3IRQ.x P3IFG.x P3SEL.x Interrupt Edge P3IES.x Select Figure 6-4. Port P3 (P3.0 to P3.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 87 Timer TA2.1 output P3.7/TA2.2 7 P3.7 (I/O) I: 0; O: 1 Timer TA2.CCI2A capture input Timer TA2.2 output Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 88 Module X IN P4IE.x P4IRQ.x P4IFG.x P4SEL.x Interrupt Edge P4IES.x Select Figure 6-5. Port P4 (P4.0 to P4.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 89 Timer TB0.TB0OUTH SVMOUT (1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 90 (6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF- reference is available at the pin. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 91 6 P5.6 (I/O) I: 0; O: 1 ADC12CLK DMAE0 P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 RTCCLK Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 92 1: High drive P6.3/CB3/A3 P6.4/CB4/A4 P6IN.x P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Keeper Figure 6-8. Port P6 (P6.0 to P6.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 93 (3) The ADC12_A channel Ax is connected internally to AV if not selected by the respective INCHx bits. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 94 P7.2/XT2IN P7DS.2 P7SEL.2 0: Low drive 1: High drive P7IN.2 Keeper Figure 6-9. Port P7 (P7.2) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 95 (3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 96 0: Low drive P7.6/CB10/A14/DAC0 1: High drive P7.7/CB11/A15/DAC1 P7IN.x Keeper Figure 6-11. Port P7 (P7.4 to P7.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 97 (3) The ADC12_A channel Ax is connected internally to AV if not selected by the respective INCHx bits. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 98 I: 0; O: 1 UCB1SOMI/UCB1SCL P8.7 P8.7 (I/O) I: 0; O: 1 (1) X = Don't care Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 99 I: 0; O: 1 P9.6 6 P9.6 (I/O) I: 0; O: 1 P9.7 7 P9.7 (I/O) I: 0; O: 1 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 100 Hi-Z Hi-Z Outputs off Outputs enabled Outputs enabled Outputs enabled Outputs enabled Direction set by USB module Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 101 PUREN Input disabled Pullup disabled Input disabled Pullup enabled Input enabled Pullup disabled Input enabled Pullup enabled Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 102 0: Low drive PJ.3/TCK 1: High drive PJIN.x To JTAG Figure 6-16. Port PJ (PJ.1 to PJ.3) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 103 (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 104 SLAS650E – JUNE 2010 – REVISED DECEMBER 2015 www.ti.com 6.14 Device Descriptors Table 6-65 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 6-65. MSP430F563x Device Descriptor Table VALUE SIZE DESCRIPTION ADDRESS (bytes)
  • Page 105 Program up to eight devices at a time. Works with a PC or as a MSP-GANG Serial and USB Texas Instruments stand-alone package. Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 106 XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633...
  • Page 107 -HT = Extreme Temperature Parts ( 55°C to 150°C) – -Q1 = Automotive Q100 Qualified Figure 7-1. Device Nomenclature Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 108 Click here Click here MSP430F5630 Click here Click here Click here Click here Click here Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633 MSP430F5632 MSP430F5631 MSP430F5630...
  • Page 109 All other trademarks are the property of their respective owners. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 110 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F5630IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR M430F5630 &...
  • Page 111 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F5633IZQWT ACTIVE Green (RoHS SNAGCU Level-3-260C-168 HR M430F5633 MICROSTAR & no Sb/Br) JUNIOR MSP430F5634IPZ ACTIVE...
  • Page 112 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F5637IZQWT NRND Call TI Call TI M430F5637 MICROSTAR JUNIOR MSP430F5638IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR...
  • Page 113 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
  • Page 114 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F5630IPZR LQFP 1000 330.0 24.4 17.0 17.0 20.0 24.0 MSP430F5630IZQWR...
  • Page 115 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F5633IPZR LQFP 1000 330.0 24.4 17.0 17.0 20.0 24.0 MSP430F5633IZQWR BGA MI 2500 330.0 16.4 12.0 16.0 CROSTA...
  • Page 116 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) MSP430F5630IPZR LQFP 1000 367.0 367.0 45.0 MSP430F5630IZQWR BGA MICROSTAR 2500 336.6 336.6 28.6 JUNIOR MSP430F5630IZQWT BGA MICROSTAR 336.6 336.6 28.6 JUNIOR MSP430F5631IPZR...
  • Page 117 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2015 Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) MSP430F5635IZQWR BGA MICROSTAR 2500 336.6 336.6 28.6 JUNIOR MSP430F5635IZQWT BGA MICROSTAR 336.6 336.6 28.6 JUNIOR MSP430F5636IZQWR BGA MICROSTAR 2500 336.6 336.6 28.6 JUNIOR MSP430F5637IPZR LQFP 1000...
  • Page 119 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 120 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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