Texas Instruments MSP430F533x Manual

Texas Instruments MSP430F533x Manual

Mixed-signal microcontrollers
Table of Contents

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1 Device Overview

1.1

Features

1
• Low Supply Voltage Range: 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode (AM):
All System Clocks Active:
270 µA/MHz at 8 MHz, 3.0 V, Flash Program
Execution (Typical)
– Standby Mode (LPM3):
Watchdog With Crystal and Supply Supervisor
Operational, Full RAM Retention, Fast Wakeup:
1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)
– Shutdown Real-Time Clock (RTC) Mode
(LPM3.5):
Shutdown Mode, Active RTC With Crystal:
1.1 µA at 3.0 V (Typical)
– Shutdown Mode (LPM4.5):
0.3 µA at 3.0 V (Typical)
• Wake up From Standby Mode in 3 µs (Typical)
• 16-Bit RISC Architecture, Extended Memory, up to
20-MHz System Clock
• Flexible Power-Management System
– Fully Integrated LDO With Programmable
Regulated Core Supply Voltage
– Supply Voltage Supervision, Monitoring, and
Brownout
• Unified Clock System
– FLL Control Loop for Frequency Stabilization
– Low-Power Low-Frequency Internal Clock
Source (VLO)
– Low-Frequency Trimmed Internal Reference
Source (REFO)
– 32-kHz Crystals (XT1)
– High-Frequency Crystals up to 32 MHz (XT2)
1.2

Applications

Analog and Digital Sensor Systems
Digital Motor Control
Remote Controls
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333
MSP430F533x Mixed-Signal Microcontrollers
Tools &
Technical
Software
Documents
SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015
• Four 16-Bit Timers With 3, 5, or 7
Capture/Compare Registers
• Two Universal Serial Communication Interfaces
(USCIs)
– USCI_A0 and USCI_A1 Each Support:
Enhanced UART Supports Automatic Baud-
Rate Detection
IrDA Encoder and Decoder
Synchronous SPI
– USCI_B0 and USCI_B1 Each Support:
2
I
C
Synchronous SPI
• Integrated 3.3-V Power System
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Shared Reference, Sample-and-Hold, and
Autoscan Feature
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• Voltage Comparator
• Hardware Multiplier Supports 32-Bit Operations
• Serial Onboard Programming, No External
Programming Voltage Needed
• Six-Channel Internal DMA
• RTC Module With Supply Voltage Backup Switch
Table 3-1
Summarizes the Available Family
Members
• For Complete Module Descriptions, See the
MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208)
Thermostats
Digital Timers
Hand-Held Meters
Support &
Community

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Summary of Contents for Texas Instruments MSP430F533x

  • Page 1: Device Overview

    Software Documents MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015 MSP430F533x Mixed-Signal Microcontrollers 1 Device Overview Features • Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7 Capture/Compare Registers •...
  • Page 2: Description

    The digitally controlled oscillator (DCO) allows the device to wake up from low- power modes to active mode in 3 µs (typical). The MSP430F533x devices are microcontrollers with an integrated 3.3-V LDO, a high-performance 12-bit ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.
  • Page 3 3 CC Registers Registers 2.5V Backup (12 ext/4 int) Port PJ Registers System Autoscan Figure 1-2. Functional Block Diagram – MSP430F5335, MSP430F5333 Device Overview Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 4: Table Of Contents

    5.27 Timer_A, Timers TA0, TA1, and TA2 ..........Glossary ........ 5.28 Timer_B, Timer TB0 Mechanical, Packaging, and Orderable ........5.29 Battery Backup Table of Contents Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 5: Revision History

    Development Tools Support, Device and Development Tool Nomenclature, ............Trademarks, and Electrostatic Discharge Caution sections to it ............. • Added Section 8, Mechanical, Packaging, and Orderable Information Revision History Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 6: Device Comparison

    For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. Device Comparison Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 7: Terminal Configuration And Functions

    P2.7/P2MAP7 P4.2/TB0.2 DVCC1 P4.1/TB0.1 NOTE: DNC = Do not connect Figure 4-1. 100-Pin PZ Package (Top View) – MSP430F5338, MSP430F5336 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 8: Pin Designation - Msp430F5335Ipz, Msp430F5333Ipz

    P2.7/P2MAP7 P4.2/TB0.2 DVCC1 P4.1/TB0.1 NOTE: DNC = Do not connect Figure 4-2. 100-Pin PZ Package (Top View) – MSP430F5335, MSP430F5333 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 9: Pin Designation - Msp430F5338Izqw

    (TOP VIEW) NOTE: For terminal assignments, see Table 4-1 Figure 4-3. 113-Pin ZQW Package (Top View) – MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 10: Signal Descriptions

    Output terminal of crystal oscillator XT1 (1) I = input, O = output, N/A = not available on this package offering Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 11 (2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C VCORE Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 12 Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output General-purpose digital I/O with port interrupt P4.6/TB0.6 Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 13 General-purpose digital I/O P7.2/XT2IN Input terminal for crystal oscillator XT2 General-purpose digital I/O P7.3/XT2OUT Output terminal of crystal oscillator XT2 Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 14 Reserved. TI recommends connecting to ground (DVSS, AVSS). (3) When this pin is configured as reset, the internal pullup resistor is enabled by default. Terminal Configuration and Functions Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 15: Specifications

    (2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 5.22 for the exact values and further details. (3) A capacitor tolerance of ±20% or better is required. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 16 0, 1, 2, 3 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 5-1. Frequency vs Supply Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 17: Active Mode Supply Current Into

    CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), f = 32768 Hz, f = 0 MHz ACLK MCLK SMCLK LDO disabled (LDOEN = 0). Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 18: Thermal Resistance Characteristics

    (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 19: Schmitt-Trigger Inputs - General-Purpose I/O

    (2) The maximum total current, I and I , for all outputs combined should not exceed ±100 mA to hold the maximum voltage (OHmax) (OLmax) drop specified. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 20: Outputs - General-Purpose I/O (Reduced Drive Strength)

    The output is connected to the center tap of the divider. (3) The output voltage reaches at least 10% and 90% V at the specified toggle frequency. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 21: Typical Characteristics - Outputs, Reduced Drive Strength (Pxds.y = 0)

    V – High-Level Output Voltage – V Figure 5-5. Typical High-Level Output Current vs High-Level Figure 5-4. Typical High-Level Output Current vs High-Level Output Voltage Output Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 22: Typical Characteristics - Outputs, Full Drive Strength (Pxds.y = 1)

    V – High-Level Output Voltage – V Figure 5-8. Typical High-Level Output Current vs High-Level Figure 5-9. Typical High-Level Output Current vs High-Level Output Voltage Output Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 23: Crystal Oscillator, Xt1, Low-Frequency Mode

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 24: Crystal Oscillator, Xt2

    (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 25: Internal Very-Low-Power Low-Frequency Oscillator (Vlo)

    (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 26: Dco Frequency

    = 1 MHz Typical DCO Frequency, V = 3.0 V, T = 25°C DCOx = 31 DCOx = 0 DCORSEL Figure 5-10. Typical DCO frequency Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 27: Pmm, Brownout Reset (Bor)

    (LPM) 1.8 V ≤ DV ≤ 3.6 V, 0 µA ≤ I(V ) ≤ 30 µA 1.44 CORE0 CORE mode, PMMCOREV = 0 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 28: Pmm, Svs High Side

    VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 29: Pmm, Svs Low Side

    LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (3) This value represents the time from the wake-up event to the reset vector execution. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 30: Timer_A, Timers Ta0, Ta1, And Ta2

    VBAT3 Charger end voltage CHVx = 2 2.65 CHVx CHCx = 1 Charge limiting resistor CHCx = 2 kΩ CHARGE CHCx = 3 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 31: Usci (Uart Mode)

    SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5- Figure 5-12. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 32 CKPL = 0 UCLK CKPL = 1 LO/HI LO/HI HD,MI SU,MI SOMI HD,MO VALID,MO SIMO Figure 5-12. SPI Master Mode, CKPH = 1 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 33: Usci (Spi Slave Mode)

    (3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-13 Figure 5-14. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 34 CKPL = 0 UCLK CKPL = 1 LO/HI LO/HI HD,SI SU,SI SIMO HD,MO STE,ACC STE,DIS VALID,SO SOMI Figure 5-14. SPI Slave Mode, CKPH = 1 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 35: Usci (I C Mode)

    2.2 V Pulse duration of spikes suppressed by input filter HD,STA SU,STA HD,STA HIGH SU,DAT SU,STO HD,DAT Figure 5-15. I C Mode Timing Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 36: 12-Bit Adc, Power Supply And Input Range Conditions

    = ln(2 ) x (R ) × C + 800 ns, where n = ADC resolution = 12, R = external source resistance Sample Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 37: 12-Bit Adc, Linearity Parameters Using An External Reference Voltage

    (4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 38: 12-Bit Adc, Temperature Sensor And Built-In

    1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature (°C) Figure 5-16. Typical Temperature Sensor Voltage Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 39: Ref, External Reference

    (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 40: Ref, Built-In Reference

    (8) The condition is that the error in a conversion started after t is less than ±0.5 LSB. The settling time depends on the external REFON capacitive load when REFOUT = 1. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 41: 12-Bit Dac, Supply Specifications

    (2) This parameter is not production tested. (3) The offset calibration works on the output operational amplifier. Offset calibration is triggered by setting the DAC12CALON bit. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 42: 12-Bit Dac, Linearity Specifications

    Ideal transfer function Offset Error Gain Error = 100 pF Load Positive Negative DAC Code Figure 5-17. Linearity Test Load Conditions and Gain/Offset Definition Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 43: 12-Bit Dac, Output Specifications

    (1) Data is valid after the offset calibration of the output amplifier. O/P(DAC12_x) Load Load DAC12 = 100 pF Load O/P(DAC12_x) AV – 0.3 V Figure 5-18. DAC12_x Output Resistance Tests Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 44: 12-Bit Dac, Reference Input Specifications

    = 3 k Energy Load Load ±1/2 LSB = 100 pF Load O/P(DAC12.x) settleLH settleHL Figure 5-19. Settling Time and Glitch Energy Testing Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 45: 12-Bit Dac, Dynamic Specifications (Continued)

    DAC12_0 DAC0 = 100 pF Load REF+ DAC12_yOUT Load Load DAC12_xOUT DAC12_1 DAC1 Toggle = 100 pF Load Figure 5-22. Crosstalk Test Conditions Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 46: Comparator_B

    (n + 0.5) (n + 1) (n + 1.5) CB_REF given tap n = 0 to 31 / 32 / 32 / 32 Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 47: Ports Pu.0 And

    V = 3.0 V T = 25ºC V – High-Level Output Voltage – V Figure 5-24. Ports PU.0, PU.1 Typical High-Level Output Characteristics Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 48: Ldo-Pwr (Ldo Power System)

    Settling time V ENABLE recommended capacitances (1) A current overload is detected when the total current supplied from the LDO exceeds this value. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 49: Flash Memory

    TEST/SBWTCK pin high before applying the SBW,En first SBWTCK clock edge. (2) f may be restricted to meet the timing requirements of the module selected. Specifications Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 50: Detailed Description

    6 Detailed Description Overview The MSP430F533x devices include an integrated 3.3-V LDO, a high-performance 12-bit ADC, a comparator, two USCIs, a hardware multiplier, DMA, four 16-bit timers, an RTC module with alarm capabilities, and up to 74 I/O pins.
  • Page 51: Instruction Set

    MOV @R10+,R11 R10 + 2 → R10 Immediate MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source, D = destination Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 52: Operating Modes

    Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wake-up signal from RST/NMI, P1, P2, P3, and P4 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 53: Interrupt Vector Addresses

    The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence (see Table 6-3). Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations SYSTEM WORD INTERRUPT SOURCE...
  • Page 54: Memory

    MSP430F5338, MSP430F5336, MSP430F5335, MSP430F5333 SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430F533x Configurations (continued) SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY INTERRUPT ADDRESS 0FFC8h Reserved Reserved ⋮ ⋮ 0FF80h 0, lowest (5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary.
  • Page 55: Bootloader (Bsl)

    For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 56: Flash Memory (Link To User's Guide)

    Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A can be locked separately. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 57: Ram (Link To User's Guide)

    The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented. There are 8 bytes of backup RAM available on MSP430F533x. It can be wordwise accessed by the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
  • Page 58 USCI_A0 UART RXD (direction controlled by USCI – input), P2.5/P2MAP5 PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI) P2.6/P2MAP6 PM_NONE DVSS P2.7/P2MAP7 PM_NONE DVSS Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 59 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 60 SVMHVLRIFG Reserved 14h to 1Eh Lowest No interrupt pending NMIIFG Highest SYSUNIV, User NMI OFIFG 019Ah ACCVIFG Reserved 08h to 1Eh Lowest Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 61 (1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not cause any DMA trigger event when selected. (2) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 62 The USCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3-pin or 4-pin) or I The MSP430F533x series includes two complete USCI modules (n = 0 to 1). 6.12.11 Timer TA0...
  • Page 63 CCR1 TA1.1 (internal) 45-P3.3 L8-P3.3 TA1.2 CCI2A 45-P3.3 L8-P3.3 ACLK CCI2B (internal) CCR2 TA1.2 (1) Only on devices with peripheral module DAC12_A. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 64 48-P3.6 L9-P3.6 TA2.1 CCI1A 48-P3.6 L9-P3.6 CBOUT CCI1B (internal) CCR1 TA2.1 49-P3.7 M10-P3.7 TA2.2 CCI2A 49-P3.7 M10-P3.7 ACLK CCI2B (internal) CCR2 TA2.2 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 65 CCI6B P2MAPx P2MAPx CCR6 TB0.6 (1) Timer functions selectable by the port mapping controller. (2) Only on devices with peripheral module DAC12_A. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 66 Up to 10 hardware triggers can be combined to form complex triggers or breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 67 000h-014h (1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 68 UCS control 3 UCSCTL3 UCS control 4 UCSCTL4 UCS control 5 UCSCTL5 UCS control 6 UCSCTL6 UCS control 7 UCSCTL7 UCS control 8 UCSCTL8 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 69 Port P1 interrupt flag P1IFG Port P2 input P2IN Port P2 output P2OUT Port P2 direction P2DIR Port P2 pullup/pulldown enable P2REN Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 70 Port P6 output P6OUT Port P6 direction P6DIR Port P6 pullup/pulldown enable P6REN Port P6 drive strength P6DS Port P6 selection P6SEL Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 71 Capture/compare 0 TA0CCR0 Capture/compare 1 TA0CCR1 Capture/compare 2 TA0CCR2 Capture/compare 3 TA0CCR3 Capture/compare 4 TA0CCR4 TA0 expansion 0 TA0EX0 TA0 interrupt vector TA0IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 72 Capture/compare control 2 TA2CCTL2 TA2 counter TA2R Capture/compare 0 TA2CCR0 Capture/compare 1 TA2CCR1 Capture/compare 2 TA2CCR2 TA2 expansion 0 TA2EX0 TA2 interrupt vector TA2IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 73 32-bit operand 1 – multiply high word MPY32H 32-bit operand 1 – signed multiply low word MPYS32L 32-bit operand 1 – signed multiply high word MPYS32H Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 74 DMA channel 3 destination address low DMA3DAL DMA channel 3 destination address high DMA3DAH DMA channel 3 transfer size DMA3SZ DMA channel 4 control DMA4CTL Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 75 USCI I2C own address UCB0I2COA USCI I2C slave address UCB0I2CSA USCI interrupt enable UCB0IE USCI interrupt flags UCB0IFG USCI interrupt vector word UCB0IV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 76 ADC memory control 4 ADC12MCTL4 ADC memory control 5 ADC12MCTL5 ADC memory control 6 ADC12MCTL6 ADC memory control 7 ADC12MCTL7 ADC memory control 8 ADC12MCTL8 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 77 Comp_B control 0 CBCTL0 Comp_B control 1 CBCTL1 Comp_B control 2 CBCTL2 Comp_B control 3 CBCTL3 Comp_B interrupt CBINT Comp_B interrupt vector word CBIV Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 78 Table 6-48. LDO and Port U Configuration Registers (Base Address: 0900h) REGISTER DESCRIPTION REGISTER OFFSET LDO key/ID LDOKEYID PU port control PUCTL LDO power control LDOPWRCTL Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 79: Input/Output Schematics

    P1.5/TA0.4 P1.6/TA0.1 P1.7/TA0.2 Module X IN P1IE.x P1IRQ.x P1IFG.x P1SEL.x Interrupt Edge P1IES.x Select Figure 6-2. Port P1 (P1.0 to P1.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 80 Timer TA0.CCI1B capture input Timer TA0.1 output P1.7/TA0.2 7 P1.7 (I/O) I: 0; O: 1 Timer TA0.CCI2B capture input Timer TA0.2 output Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 81 P2.5/P2MAP5 P2.6/P2MAP6 P2.7/P2MAP7 To Port Mapping P2IE.x P2IRQ.x P2IFG.x P2SEL.x Interrupt Edge P2IES.x Select Figure 6-3. Port P2 (P2.0 to P2.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 82 Mapped secondary digital function ≤ 19 P2.7/P2MAP7 7 P2.7 (I/O) I: 0; O: 1 Mapped secondary digital function ≤ 19 (1) X = Don't care Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 83 P3.5/TA2.0 P3.6/TA2.1 P3.7/TA2.2 Module X IN P3IE.x P3IRQ.x P3IFG.x P3SEL.x Interrupt Edge P3IES.x Select Figure 6-4. Port P3 (P3.0 to P3.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 84 Timer TA2.CCI1A capture input Timer TA2.1 output P3.7/TA2.2 7 P3.7 (I/O) I: 0; O: 1 Timer TA2.CCI2A capture input Timer TA2.2 output Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 85 P4.5/TB0.5 P4.6/TB0.6 P4.7/TB0OUTH/SVMOUT Module X IN P4IE.x P4IRQ.x P4IFG.x P4SEL.x Interrupt Edge P4IES.x Select Figure 6-5. Port P4 (P4.0 to P4.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 86 I: 0; O: 1 SVMOUT Timer TB0.TB0OUTH SVMOUT (1) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 87 (6) Setting the P5SEL.1 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF- reference is available at the pin. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 88 I: 0; O: 1 P5.6/ADC12CLK/DMAE0 6 P5.6 (I/O) I: 0; O: 1 ADC12CLK DMAE0 P5.7/RTCCLK 7 P5.7 (I/O) I: 0; O: 1 RTCCLK Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 89 0: Low drive P6.2/CB2/A2 1: High drive P6.3/CB3/A3 P6.4/CB4/A4 P6IN.x P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Keeper Figure 6-8. Port P6 (P6.0 to P6.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 90 (2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AV if not selected by the respective INCHx bits. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 91 To XT2 P7REN.2 P7DIR.2 P7OUT.2 P7.2/XT2IN P7DS.2 P7SEL.2 0: Low drive 1: High drive P7IN.2 Keeper Figure 6-9. Port P7 (P7.2) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 92 (3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 93 P7.4/CB8/A12 P7DS.x P7.5/CB9/A13 P7SEL.x 0: Low drive P7.6/CB10/A14/DAC0 1: High drive P7.7/CB11/A15/DAC1 P7IN.x Keeper Figure 6-11. Port P7 (P7.4 to P7.7) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 94 (2) Setting the P7SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AV if not selected by the respective INCHx bits. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 95 I: 0; O: 1 UCB1SIMO/UCB1SDA P8.6/UCB1SOMI/UCB1SCL P8.6 (I/O) I: 0; O: 1 UCB1SOMI/UCB1SCL P8.7 P8.7 (I/O) I: 0; O: 1 (1) X = Don't care Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 96 5 P9.5 (I/O) I: 0; O: 1 P9.6 6 P9.6 (I/O) I: 0; O: 1 P9.7 7 P9.7 (I/O) I: 0; O: 1 Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 97 (1) PU.1 and PU.0 inputs and outputs are supplied from LDOO. LDOO can be generated by the device using the integrated 3.3-V LDO when enabled. LDOO can also be supplied externally when the 3.3-V LDO is not being used and is disabled. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 98 PJDS.x PJ.2/TMS From JTAG 0: Low drive PJ.3/TCK 1: High drive PJIN.x To JTAG Figure 6-16. Port PJ (PJ.1 to PJ.3) Schematic Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 99 (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. Detailed Description Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 100: Device Descriptors

    SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com 6.14 Device Descriptors Table 6-62 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 6-62. MSP430F533x Device Descriptor Table VALUE SIZE DESCRIPTION ADDRESS (bytes)
  • Page 101: Device And Documentation Support

    Program up to eight devices at a time. Works with a PC or as a MSP-GANG Serial and USB Texas Instruments stand-alone package. Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 102 MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 103 – -HT = Extreme Temperature Parts ( 55°C to 150°C) – -Q1 = Automotive Q100 Qualified Figure 7-1. Device Nomenclature Device and Documentation Support Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5338 MSP430F5336 MSP430F5335 MSP430F5333...
  • Page 104: Documentation Support

    SLAS721D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com Documentation Support The following documents describe the MSP430F533x devices. Copies of these documents are available on the Internet at www.ti.com. SLAU208 MSP430x5xx and MSP430x6xx Family User's Guide. Detailed information on the modules and peripherals available in this device family.
  • Page 105: Glossary

    All other trademarks are the property of their respective owners. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 106 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F5333IPZ ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5333 &...
  • Page 107 PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2015 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F5338IZQWT ACTIVE Green (RoHS SNAGCU Level-3-260C-168 HR M430F5338 MICROSTAR & no Sb/Br) JUNIOR The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 108 PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F5333IZQWR BGA MI 2500 330.0 16.4 12.0 16.0 CROSTA R JUNI...
  • Page 109 PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2015 Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F5338IZQWT BGA MI 330.0 16.4 12.0 16.0 CROSTA R JUNI *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm)
  • Page 111 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 112 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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