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Texas Instruments CC2538 User Manual

Texas Instruments CC2538 User Manual

System-on-chip solution for 2.4-ghz ieee 802.15.4 and zigbee/zigbee ip applications

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CC2538 System-on-Chip Solution for 2.4-GHz

IEEE 802.15.4 and ZigBee®/ZigBee IP®

Applications

Texas Instruments CC2538™ Family of Products

Version B

User's Guide

Literature Number: SWRU319B

April 2012 – Revised April 2013

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Page 1 Public Version CC2538 System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee®/ZigBee IP® Applications Texas Instruments CC2538™ Family of Products Version B User's Guide Literature Number: SWRU319B April 2012 – Revised April 2013...
Page 2 WARNING: EXPORT NOTICE Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S.
Page 3: Table Of Contents
The Cortex-M3 Processor Introduction ......................Block Diagram ........................Overview ..................2.3.1 System-Level Interface ................. 2.3.2 Integrated Configurable Debug ..................2.3.3 Trace Port Interface Unit SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 4 3.2.4.1.2 Updating an MPU Region Using Multiple-Word Writes ....................3.2.4.1.3 Subregions ..............3.2.4.2 MPU Access Permission Attributes ..........3.2.4.2.1 MPU Configuration for a CC2538 Microcontroller ..................... 3.2.4.3 MPU Mismatch ....................... Register Map ................... SysTick Register Descriptions ....................NVIC Register Descriptions ............
Page 5 Power-On Reset and Brownout Detector .................... 7.4.3 Clock Loss Detector ....................Emulator in Power Modes ....................Chip State Retention ................7.6.1 CRC Check on State Retention SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 6 9.3.1.1.2 GPIO Instances Register Mapping Summary ..............9.3.1.2 GPIO Common Register Descriptions ....................9.3.2 IOC Registers ..............9.3.2.1 IOC Registers Mapping Summary Contents SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 7 General-Purpose Timers ....................11.1 General-Purpose Timers ......................11.2 Block Diagram ....................11.3 Functional Description ..................11.3.1 GPTM Reset Conditions ....................11.3.2 Timer Modes SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 8 13.4.1.1 SMWDTHROSC Registers Mapping Summary ..............13.4.1.2 SMWDTHROSC Register Descriptions ......................Watchdog Timer ......................14.1 Watchdog Timer ..................... 14.2 Watchdog Timer Registers ................... 14.2.1 SMWDTHROSC Registers Contents SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 9 18.4.4.2 Flow Control ............18.4.4.2.1 Hardware Flow Control (RTS and CTS) ..................... 18.4.5 LIN Support ....................18.4.5.1 LIN Master ....................18.4.5.2 LIN Slave SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 10 19.4.2.1 Transmit FIFO ..................... 19.4.2.2 Receive FIFO ......................19.4.3 Interrupts ....................19.4.4 Frame Formats ..........19.4.4.1 Texas Instruments Synchronous Serial Frame Format ................19.4.4.2 Freescale SPI Frame Format ................19.4.4.2.1 SPO Clock Polarity Bit ................19.4.4.2.2 SPH Phase Control Bit .........
Page 11 22.1.1 Terms and Conventions Used in this Manual ....................22.1.1.1 Acronyms ................22.1.1.2 Formulae and Nomenclature ......................22.1.2 Overview ....................22.1.2.1 Feature List SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 12 22.2.1.1.2 Key Store .................. 22.2.1.1.3 AES Crypto Engine ................22.2.1.1.4 SHA-256 Hash Engine ..............22.2.1.1.5 Master Control and Interrupts ................... 22.2.1.1.6 Debug Capabilities Contents SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 13 22.2.5.2.1 Regular use ................. 22.2.5.2.2 Interrupting DMA Transfers ............22.2.5.2.3 Interrupts and HW/SW Synchronization ....................22.2.5.3 Hashing ............... 22.2.5.3.1 Data Format and Byte Order SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 14 22.4.2.1 PKA Registers Mapping Summary ................22.4.2.2 PKA Register Descriptions ..........................Radio ........................23.1 RF Core ......................23.1.1 Interrupts ..................... 23.1.2 Interrupt Registers Contents SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 15 23.10 RX FIFO Access ................ 23.10.1 Using the FIFO and FIFOP Signals ....................23.10.2 Error Conditions ......................23.10.3 RSSI ..................23.10.4 Link Quality Indication SWRU319B – April 2012 – Revised April 2013 Contents Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 16 23.14.9.33 ISSTART ....................23.14.9.34 ISRXON ..................23.14.9.35 ISRXMASKBITSET ..................23.14.9.36 ISRXMASKBITCLR ....................23.14.9.37 ISTXON .................... 23.14.9.38 ISTXONCCA ..................23.14.9.39 ISSAMPLECCA ....................23.14.9.40 ISRFOFF Contents SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 17 SmartRF™ Studio Software for Evaluation (www.ti.com/smartrfstudio) .................. TIMAC Software (www.ti.com/timac) ................Z-Stack™ Software (www.ti.com/z-stack) ........................Abbreviations ...................... Additional Information ................. Texas Instruments Low-Power RF Web Site ..................Low-Power RF Online Community ............. Texas Instruments Low-Power RF Developer Network ..................... Low-Power RF eNewsletter ........................References ......................
Page 18 19-3. TI Synchronous Serial Frame Format (Continuous Transfer) ..........19-4. Freescale SPI Format (Single Transfer) With SPO = 0 and SPH = 0 List of Figures SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 19 23-4. Format of the Frame Control Field (FCF) ................... 23-5. Frame Data Written to the TX FIFO ........................23-6. TX Flow SWRU319B – April 2012 – Revised April 2013 List of Figures Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 20 23-19. FFT of the Random Bytes ........23-20. Histogram of 20 Million Bytes Generated With the RANDOM Instruction ....................23-21. Running a CSP Program List of Figures SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 21 TEX, S, C, and B Bit Field Encoding ................3-4. Cache Policy for Memory Attribute Encoding ..................... 3-5. AP Bit Field Encoding ............3-6. Memory Region Attributes for a CC2538 Microcontroller ....................3-7. Peripherals Register Map ......................4-1. Memory Map ....................4-2.
Page 22 22-8. ExpMod Result Vector/Scratchpad Area Memory Allocation ............ 22-9. ExpMod Scratchpad Area / Input Vector Overlap Restrictions ..............22-10. Required PKA RAM Sizes for Exponentiations List of Tables SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 23 22-56. Valid Combinations for CTRL_ALG_SEL Flags ..................22-57. Master Control Algorithm Select ......................22-58. Software Reset ....................22-59. Interrupt Configuration SWRU319B – April 2012 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 24 ..............23-2. Frame Filtering and Source Matching Memory Map ............... 23-3. IEEE 802.15.4-2006 Symbol-to-Chip Mapping ..................... 23-4. FSM State Mapping List of Tables SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 25 .................. 23-8. RFCORE_FFSM Register Summary .................. 23-9. RFCORE_XREG Register Summary ................... 23-10. CCTEST Register Summary ..................23-11. ANA_REGS Register Summary SWRU319B – April 2012 – Revised April 2013 List of Tables Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 26: Preface
SWRU319B – April 2012 – Revised April 2013 Read This First About This Document This user's guide provides information on how to use the CC2538 and describes the functional blocks of the system-on-chip (SoC) designed around the ARM® Cortex™-M3 core and an IEEE 802.15.4 radio. Audience This manual is intended for system software developers, hardware designers, and application developers.
Page 27 (see SIGNAL and SIGNAL below). Change the value of the signal from the logically True state to deassert a signal the logically False state. SWRU319B – April 2012 – Revised April 2013 Read This First Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 28 TI’s ZigBee PRO stack Z-Stack™ with associated profiles and the ZigBee IP stack with Smart Energy 2.0 profile. The usage is, however, not limited to these protocols alone. The CC2538 is, for example, also suitable for 6LoWPAN and wireless HART implementations.
Page 29 After each register description, a table summarizes all hyperlinked register calls. To navigate in the PDF documents, see Acrobat Reader Tips. SWRU319B – April 2012 – Revised April 2013 Read This First Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 30 Beginning or end of two or more simultaneous operations Flow Line Lines indicate the sequence of steps and the direction of flow. Read This First SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 31 Click the Go To Previous View button or the Go To Next View button. NOTE: This navigation tip is useful to return to your previous view after clicking on a register call hyperlink. SWRU319B – April 2012 – Revised April 2013 Read This First Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 32: Architectural Overview
SWRU319B – April 2012 – Revised April 2013 Architectural Overview The CC2538 device family provides solutions for a wide range of applications. To help the user develop these applications, this user's guide focuses on the use of the different building blocks of the CC2538 device family.
Page 33: Target Applications
Public Version Target Applications www.ti.com Target Applications The CC2538 family is positioned for low-power wireless applications such as: • IEEE 802.15.4 Radio Networks • ZigBee Smart Energy 1.x and to 2.0 profiles • Home and building automation • Intelligent lighting systems •...
Page 34: Cc2538 Block Diagram
Power-on reset and brown-out MAC timer detection Low-power RF chain comparator Modulator Demod 12-bit ADC With Temp Sensor Figure 1-1. CC2538 Block Diagram Architectural Overview SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 35 CC2538 device to a low-power state during extended periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (which is a real-time clock [RTC]) with interrupt and 16KB of RAM with retention in all power modes positions the CC2538 microcontroller perfectly for battery applications.
Page 36: Functional Overview
1.3.1.2 Memory Map A memory map lists the location of instructions and data in memory. The memory map for the CC2538 can be found in the Memories section of this User's Guide. Register addresses are given as a hexadecimal increment, relative to the base address of the module as shown in the memory map.
Page 37: Nested Vector Interrupt Controller
The following sections describe the on-chip memory modules. 1.3.2.1 SRAM The CC2538 provides a 16KB block of single-cycle on-chip SRAM with full retention in all power modes. In addition, some variants offer an additional 16KB of single-cycle on-chip SRAM without retention in the lowest power modes.
Page 38: Rom
1.3.2.3 The ROM is preprogrammed with a serial boot loader (SPI or UART). For applications that require in-field programmability, the royalty-free CC2538 boot loader can act as an application loader and support in-field firmware updates. 1.3.3 Radio The CC2538 device family provides a highly integrated low-power IEEE 802.15.4-compliant radio transceiver.
Page 39: Mac Timer
A watchdog timer is used to regain control when a system fails due to a software error or because an external device does not respond in the expected way. When enabled by software, the watchdog timer must be cleared periodically; otherwise, the watchdog timer resets the CC2538 device when it times out. 1.3.5.3...
Page 40: System Control And Clock
1.3.7 System Control and Clock System control determines the overall operation of the CC2538 device. System control provides information about the CC2538 device, controls power-saving features, controls the clocking of the CC2538 device and individual peripherals, and handles reset detection and reporting.
Page 41: Serial Communications Peripherals
Universal serial bus (USB) is a serial bus standard designed to allow peripherals to be connected and disconnected using a standardized interface. The CC2538 device supports the USB 2.0 FS configuration in device mode and has the following features: •...
Page 42: I 2 C
Both the I C master and slave can generate interrupts. The CC2538 microcontroller includes an I C module with the following features: •...
Page 43: Ssi
FIFO contains four entries 1.3.9 Programmable GPIOs GPIO pins offer flexibility for a variety of connections. The CC2538 GPIO module is comprised of four GPIO blocks, each corresponding to an individual GPIO port. The GPIO module supports CC2538 programmable I/O pins. The number of GPIOs available depends on the peripherals being used (see Chapter 5 for the signals available to each GPIO pin).
Page 44: Adc
An analog comparator is a peripheral that compares two analog voltages, two external pin inputs, and provides a logical output that signals the comparison result. The CC2538 microcontroller provides an independent integrated and low-power analog comparator that can be active in all power modes. The comparator output is mapped into the digital I/O port, and the MCU can treat the comparator output as a regular digital input.
Page 45: The Cortex-M3 Processor
........................... Topic Page ..............The Cortex-M3 Processor Introduction ....................Block Diagram ......................Overview ..................Programming Model ..................Instruction Set Summary SWRU319B – April 2012 – Revised April 2013 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 46: The Cortex-M3 Processor Introduction
32-MHz operation • 1.25 DMIPS/MHz The CC2538 builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. This chapter provides information on the CC2538 implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management.
Page 47: Overview
The Cortex-M3 processor closely integrates a nested vector interrupt controller (NVIC) to deliver industry- leading interrupt performance. The CC2538 NVIC includes a nonmaskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
Page 48: Trace Port Interface Unit
This section describes the Cortex-M3 programming model. In addition to the descriptions of the individual core registers, information about the processor modes and privilege levels for software execution and stacks is included. The Cortex-M3 Processor SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 49: Processor Mode And Privilege Levels For Software Execution
N/A (not applicable) and there is no offset. SWRU319B – April 2012 – Revised April 2013 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 50: Cortex-M3 Register Set
Cortex general-purpose register 10 Purpose Register 10 (R10). Cortex General- – – Cortex general-purpose register 11 Purpose Register 11 (R11). The Cortex-M3 Processor SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 51: Register Descriptions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA SWRU319B – April 2012 – Revised April 2013 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 52 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 53 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 54 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31:0 DATA Register data — SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 55 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LINK Bits Field Name Description Type Reset 31:0 LINK This field is the return address. 0xFFFF FFFF SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 56: Psr Register Combinations
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Q ICI / IT RESERVED ICI / IT ISRNUM SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 57 For more information, see Section 5.2.4. The value of this bit is meaningful only when accessing PSR or EPSR. 23:16 RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 58 Interrupt vector 54 0x47- Reserved 0x7F For more information, see Section 5.1.2. The value of this field is meaningful only when accessing PSR or IPSR. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 59 Prevents the activation of all exceptions except for NMI. No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 60 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 61: Exceptions And Interrupts
{Rd,} Rn , #imm12 N, Z, C, V Rd, label Load PC-relative address – AND, ANDS {Rd,} Rn, Op2 Logical AND N, Z, C SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 62 N, Z, C Multiply with accumulate, 32-bit Rd, Rn, Rm, Ra – result Multiply and subtract, 32-bit Rd, Rn, Rm, Ra – result SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 63 Store register signed halfword – STRT Rt, [Rn {, #offset}] Store register word – SUB, SUBS {Rd,} Rn, Op2 Subtract N, Z, C, V SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 64 Zero extend a byte – UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword – – Wait for event – – Wait for interrupt – SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 65: Cortex™-M3 Peripherals
........................... Topic Page ..............Cortex™-M3 Peripherals Introduction ..................Functional Description ....................Register Map ................SysTick Register Descriptions ................NVIC Register Descriptions SWRU319B – April 2012 – Revised April 2013 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 66: Cortex™-M3 Peripherals Introduction
Public Version Cortex™-M3 Peripherals Introduction www.ti.com Cortex™-M3 Peripherals Introduction This chapter provides information on the CC2538 implementation of the Cortex-M3 processor peripherals, including: • System timer (SysTick) (see SysTick): Provides a simple, 24-bit clear-on-write, decrementing, wrap-on- zero counter with a flexible control mechanism.
Page 67: Nvic
The NVIC detects that the interrupt signal is asserted and the interrupt is not active. • The NVIC detects a rising edge on the interrupt signal. SWRU319B – April 2012 – Revised April 2013 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 68: Scb
Section 4.1.1). Table 3-2 shows the possible MPU region attributes. For guidelines for programming a microcontroller implementation, see MPU Configuration for a CC2538 Microcontroller. Cortex™-M3 Peripherals SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 69: Updating An Mpu Region
MPU settings. • After MPU setup, if it includes memory transfers that must use the new MPU settings. SWRU319B – April 2012 – Revised April 2013 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 70: Updating An Mpu Region Using Multiple-Word Writes
1 apply to the first 128-KB region, configure the SRD field for region 2 to 0x03 to disable the first two subregions, as Figure 3-1 shows. Cortex™-M3 Peripherals SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 71: Mpu Access Permission Attributes
TEX, C, B, and S access permission bits. All encodings are shown for completeness; however, the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. For information on programming the MPU for CC2538 implementations, see MPU Configuration for a CC2538 Microcontroller.
Page 72: Mpu Configuration For A Cc2538 Microcontroller
Read-only, by privileged or unprivileged software 3.2.4.2.1 MPU Configuration for a CC2538 Microcontroller CC2538 microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6. Table 3-6. Memory Region Attributes for a CC2538 Microcontroller In current CC2538 microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior.
Page 73: Peripherals Register Map
0x0000 0000 Interrupt 64–95 Active Interrupt 64–95 Active Bit (ACTIVE2) 0x30C ACTIVE3 0x0000 0000 Interrupt 96–127 Active Interrupt 96–127 Active Bit (ACTIVE3) SWRU319B – April 2012 – Revised April 2013 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 74 PRI35 0x0000 0000 Interrupt 140–143 Interrupt 140–143 Priority (PRI35) Priority 0x490 PRI36 0x0000 0000 Interrupt 144–147 Interrupt 144–147 Priority (PRI36) Priority Cortex™-M3 Peripherals SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 75: Systick Register Descriptions
Size Alias 3 3 (MPUATTR3) SysTick Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. SWRU319B – April 2012 – Revised April 2013 Cortex™-M3 Peripherals Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 76 RESERVED Reserved 0x000 CLK_SRC Clock source Value Description External reference clock (not implemented for CC2538 microcontrollers) System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. INTEN Interrupt enable...
Page 77: Nvic Register Descriptions
Ensure that software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 78: Interrupt Enable
On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can be cleared only by setting the corresponding INT[n] bit in the DIS1 register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 79 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. A bit can be cleared only by setting the corresponding INT[n] bit in the DISn register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 80 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 81 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN2 register, disabling interrupt [n] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 82 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN4 register, disabling interrupt [n] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 83 If the corresponding interrupt is already pending, setting a bit has no effect. A bit can be cleared only by setting the corresponding INT[n] bit in the UNPEND1 register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 84 If the corresponding interrupt is already pending, setting a bit has no effect. A bit can be cleared only by setting the corresponding INT[n] bit in the UNPEND3 register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 85 PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 86 PEND2 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 87 PEND4 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 88 Reset 31:0 Interrupt active 0x0000 0000 Value Description The corresponding interrupt is not active. The corresponding interrupt is active, or active and pending. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 89 Reset 31:0 Interrupt active 0x0000 0000 Value Description The corresponding interrupt is not active. The corresponding interrupt is active, or active and pending. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 90 (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 91 (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 20:16 RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 92 (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 12:8 RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 93 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 94 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 95 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 96 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 97 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 98 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 99 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 100 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 101 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 102 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 103 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 104 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 105 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 106 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 107 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 108 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 109 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 110 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 111 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 112 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 113 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 114 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 115 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 116 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 117 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 118 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 119 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 120 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 121 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 122 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 123 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 124 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 125 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 126 [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 127: System Control Block (Scb) Register Descriptions
RESERVED Bits Field Name Description Type Reset 31:3 RESERVED Reserved 0x0000 0000 DISFOLD Disable IT folding Value Description No effect Disables IT folding SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 128 Description 0xC23 Cortex-M3 processor. Revision number Value Description The pn value in the rnpn product revision identifier; for example, the 0 in r2p0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 129 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. This bit is cleared by writing 1 to the PENDSTCLR bit. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 130 Description There are preempted active exceptions to execute. There are no active exceptions, or the currently executing exception is the only active exception. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 131 [7:5] INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 132 This field is used to guard against accidental writes to this register. 0x05FA must be written to this field to change the bits in this register. On a read, 0xFA05 is returned. ENDIANESS Data endianness The CC2538 implementation uses only little-endian mode so this is cleared to 0. 14:11 RESERVED Reserved...
Page 133 ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. RESERVED Reserved SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 134 Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. Reserved Reserved MAINPEND Allow main interrupt trigger SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 135 This field configures the priority level of the memory management fault. Configurable priority values are in the range 0–7, with lower values having higher priority. RESERVED Reserved SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 136 This field configures the priority level of debug. Configurable priority values are in the range 0–7, with lower values having higher priority. RESERVED Reserved 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 137 MEMP Memory management fault pending Value Description A memory management fault exception is not pending. A memory management fault exception is pending. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 138 Caution above before setting this bit. MEMA Memory management fault active Value Description Memory management fault is not active. Memory management fault is active. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 139 Value Description No unaligned access fault has occurred, or unaligned access trapping is not enabled. The processor has made an unaligned memory access. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 140 The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. The FAULTADDR register is holding a valid fault address. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 141 This bit is cleared by setting it to 1. IBUS Instruction bus error R/W1C Value Description An instruction bus error has not occurred. An instruction bus error has occurred. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 142 Value Description An instruction access violation has not occurred. The processor tried an instruction fetch from a location that does not permit execution. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 143 When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by setting it to 1. RESERVED Reserved SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 144: Mpu Register Descriptions
This section lists and describes the MPU registers, in numerical order by address offset. The MPU registers can be accessed only from privileged mode. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 145 Indicates there are eight supported MPU data regions. RESERVED Reserved 0x00 SEPARATE Separate or unified MPU Value Description Indicates the MPU is unified. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 146 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. ENABLE MPU enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 147 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ADDR REGION SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 148 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 149 On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 150 Maximum possible size occupies the complete memory map. This refers to the N parameter in the MPUBASE register (see MPU Region Base Address (MPUBASE)). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 151 The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. For more information, see Example SIZE Field Values. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 152 For information on using this bit field, see Table 3-5. 23:22 RESERVED Reserved 21:19 Type extension mask For information on using this bit field, see Table 3-3. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 153 Maximum possible size occupies the complete memory map. This refers to the N parameter in the MPUBASE register (see MPU Region Base Address (MPUBASE)). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 154 The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. For more information, see Example SIZE Field Values. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 155 For information on using this bit field, see Table 3-5. 23:22 RESERVED Reserved 21:19 Type extension mask For information on using this bit field, see Table 3-3. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 156 MPUNUMBER register. For more information, see Example SIZE Field Values. ENABLE Region enable Value Description The region is disabled. The region is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 157: Memory Map
SWRU319B – April 2012 – Revised April 2013 Memory Map This chapter describes the memory map..........................Topic Page ....................Memory Model SWRU319B – April 2012 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 158: Memory Model
The processor has a fixed memory map that provides up to 4GB of addressable memory. Table 4-1 provides the memory map for the CC2538 controller. In this manual, register addresses are given as a hexadecimal increment, relative to the base address of the module, as shown in the memory map.
Page 159: Memory Regions, Types, And Attributes
An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only when an instruction is executed from an XN region. SWRU319B – April 2012 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 160: Memory System Ordering Of Memory Accesses
For more information on memory types and the XN attribute, see Section 4.1.1, Memory Regions, Types, and Attributes. CC2538 devices may have reserved memory areas within the address ranges listed in Table 4-2...
Page 161: Bit-Banding
A word access to a bit-band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit-band accesses to match the access requirements of the underlying peripheral. SWRU319B – April 2012 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 162: Sram Memory Bit-Banding Regions
The alias word at 0x2200 001C maps to bit 7 of the bit-band byte at 0x2000 0000: 0x2200 001C = 0x2200 0000 + (0*32) + (7*4) Memory Map SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 163: Directly Accessing An Alias Region
(LSByte) of a word stored at the lowest-numbered byte, and the most-significant byte (MSByte) stored at the highest-numbered byte. Figure 4-2 shows how data is stored. SWRU319B – April 2012 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 164: Synchronization Primitives
Load-Exclusive instruction. The processor removes its exclusive access tag if one of the following conditions occurs: • The processor executes a CLREX instruction. Memory Map SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 165 An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex-M3 Instruction Set Technical User's Manual. SWRU319B – April 2012 – Revised April 2013 Memory Map Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 166: Interrupts
SWRU319B – April 2012 – Revised April 2013 Interrupts This chapter describes the interrupts..........................Topic Page ....................Exception Model ....................Fault Handling Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 167: Exception Model
The CC2538 has 48 interrupts that are spread across a range of 147 possible ARM® Cortex™-M3 interrupt inputs in a regular interrupt map setting.
Page 168 In the system, peripherals use interrupts to communicate with the processor. Table 5-2 lists the interrupts on the CC2538 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.
Page 169: Interrupts
GPTimer 0B 0x0000 0094 GPTimer 1A 0x0000 0098 GPTimer 1B 0x0000 009C GPTimer 2A 0x0000 00A0 GPTimer 2B 0x0000 00A4 Analog Comparator SWRU319B – April 2012 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 170 0x0000 0158 Reserved 0x0000 015C Reserved 0x0000 0160 Reserved 0x0000 0164 Reserved 0x0000 0168 Reserved 0x0000 016C Reserved 0x0000 070 Reserved 170 Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 171 Reserved 0x0000 0274 Reserved 0x0000 0278 Reserved 0x0000 027C Reserved 0x0000 0280 Reserved 0x0000 0284 Reserved 0x0000 0288 Reserved 0x0000 028C Reserved SWRU319B – April 2012 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 172: Exception Handlers
The least-significant bit (LSB) of each vector must be 1, indicating that the exception handler is Thumb code. ® Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 173: Exception Priorities
Interrupt 0–3 Priority (PRI0). Configurable priority values for the CC2538 implementation are in the range 0 to 7. NOTE: This means that the Reset and Hard fault exceptions, with fixed negative priority values, always have higher priority than any other exception.
Page 174: Interrupt Priority Grouping
This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 175: Exception Return
Reserved Return to Thread mode. 0xFFFF FFF9 Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF FFFA–0xFFFF FFFC Reserved SWRU319B – April 2012 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 176: Fault Handling
Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 176 Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 177: Fault Status And Fault Address Registers
Bus Fault Address (FAULTSTAT) Bus fault (BFAULTSTAT) (FAULTADDR) Bus Fault Address (FAULTADDR) Usage Fault Status Configurable Fault Status Usage fault – (UFAULTSTAT) (FAULTSTAT) SWRU319B – April 2012 – Revised April 2013 Interrupts Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 178: Lockup
That is, an pended interrupt can occur as soon as the PKA interrupt is enabled, even when the PKA is busy. The PKA ISR can test bit 15 of the PKA_FUNCTION register to confirm that the PKA interrupt is actually active. Interrupts SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 179: Jtag Interface
Switching Debug Interface from 2-pin cJTAG to 4-pin JTAG ..................Debugger Connection ..................Primary Debug Support ............Debug Access Security Through ICEPick ..................CM3 Debug Interrupt SWRU319B – April 2012 – Revised April 2013 JTAG Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 180: Test/Debug System Top Level Diagram
TCK signal is low. Logic inside the chip maintains the signal level while the TCK signal is high. JTAG Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 181: Ieee 1149.7 Features Subset
The TMS sequence from Run-Test-Idle is (1 1 0 0*n 1 1 1 0 1 0) for the IR shift to end in Pause DR. The TMS sequence from Pause DR to Pause DR is (1 1 1 0 1 0) (Done twice). SWRU319B – April 2012 – Revised April 2013 JTAG Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 182 TDO. No additional steps are required by the user to have TDI and TDO mapped as GPIO. Previous configurations of PB6 and PB7 will be overridden. JTAG Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 183: Debugger Connection
On the device, CM3 is the only debug TAP connected to the ICEPick. The CM3 DAP can be accessed using ICEPick with secondary debug TAP 0 ID. SWRU319B – April 2012 – Revised April 2013 JTAG Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 184: Primary Debug Support
Following 0x0E IR, the data register read (DR) reflects status of various activities related to the flash mass erase command. Table 6-4 shows the description. JTAG Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 185: Data Register Description For Instruction 0X0E(Read Only)
1 - Assert an interrupt to CM3 (pulling the signal high) 0 - De-assert interrupt to CM3 (pulling the signal down) SWRU319B – April 2012 – Revised April 2013 JTAG Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 186: System Control
SWRU319B – April 2012 – Revised April 2013 System Control The system control module configures the overall operation of the CC2538 device. Configurable features include reset control, power control, clock control, and low-power modes. Low-power operation is enabled through different operating modes (power modes). Ultralow-power operation is obtained by turning off the power supply to modules to avoid static (leakage) power consumption and also by using clock gating and turning off oscillators to reduce dynamic power consumption.
Page 187: Power Management
This section describes how to manage the different power saving actions. 7.1.1 Control Inputs to Power Management CC2538 has different configuration registers and an initiator (WFI instruction) for control of operational (i.e power) modes. 7.1.1.1 Clock Gating Registers The description of the clock gating registers for each peripheral are found in the register section (see ).
Page 188: Flow Diagram For Operational Modes
Sequencing time Functional limitations Active Clock gating with RCGC None None Sleep Clock gating with SCGC Enter: immediate CPU in sleep 188 System Control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 189: Sequencing When Using Power Modes
7.1.2.3.2. 7.1.2.1 Sequencing when using Power Modes When using power management in CC2538 it is important to understand the sequence of events and timing involved in the process. A simple flow diagram for power management is shown in Figure 7-2. As can be seen from the figure PM1, 2 and 3 are always entered from a state where the CPU is running on 16 MHz RCOSC.
Page 190: Simple Flow Diagram For Power Management
Active mode to PM1, PM2 or PM3. As seen in Figure 7-2 the power down sequence to PM1, PM2 and PM3 from Active mode always System Control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 191: Enter Power Mode When Running On 16 Mhz System Clock
WFI was asstered. Figure 7-3 show an example of a sequence when CC2538 is in Active mode running on 32 MHz system clock, until the chip has entered PM1, PM2 or PM3. SWRU319B – April 2012 – Revised April 2013...
Page 192: Timing Example For Transition From 32 Mhz To Pm's
After calibration is finished both clock sources are running and a switch from 32 MHz to 16 MHz can start and will occur immediately (~0.3us). System Control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 193: Exit From Power Modes
PM2 and PM3 the required time for restore that is driven by 16 MHz clock (approx 30us) will be saved. 7.1.2.4.2 32 MHz Qualification Time In the CC2538 an additional module for detection of 32 MHz XOSC stability is available. Enabling this feature adds approx 20 us to the 32 MHz XOSC startup time, see 7.2.1 for details.
Page 194: Simplified Figure Of Current Consumption In Pm1
PM3 is the most effective power saving mode but can only wake up from pin interrupts (Sleep Mode Timer is disabled) System Control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 195: Block Diagram Oscillators And Clocks
Figure 7-6. Block Diagram Oscillators and Clocks 7.2.1 High Frequency Oscillators Figure 7-6 gives an overview of the clock system with available clock sources on the CC2538 device. Two high-frequency oscillators are present in the device: • 32 MHz crystal oscillator •...
Page 196: Mhz Rcosc Calibration
32 MHz XOSC (such as the radio) are started. In the CC2538, an additional module for detection of 32 MHz XOSC stability is available. This amplitude detector can be useful in environments with significant noise on the power supply to ensure that the clock source is not used until the clock signal is stable.
Page 197: Clock Gate Matrix
Forcing the RESET_N input pin low • A POR condition • A brownout reset (BOD) condition • Watchdog timer reset condition SWRU319B – April 2012 – Revised April 2013 System Control Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 198: Reset Of Peripherals
Clock-loss detetector is disabled. During reset, the GPIO pins are configured as inputs with pull-up. In the CC2538, a system reset can be generated immediately in software by writing the NVIC_APINT_SYSRESETREQ bit to '1' in the NVIC_APINT register (see Application Interrupt and Reset Control (APINT) for the register description).
Page 199: Sys_Ctrl Register Summary
During entry/exit to/from PM2 and PM3 the device state is stored during power down and read back during power up are CRC checked. A feature to automatically reset the CC2538 in the case of a CRC error can be enabled by setting bit CRC_REN_RF and CRC_REN_USB to '1' in the SRCRC register.
Page 200 0x400D 2080 SYS_CTRL_CLD 0x0000 003F 0x94 0x400D 2094 SYS_CTRL_IWE 0x0000 0000 0x98 0x400D 2098 SYS_CTRL_I_MAP 0x0000 0000 0xA8 0x400D 20A8 SYS_CTRL_RCGC 200 System Control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 201: Sys_Ctrl Register Descriptions
Instance SYS_CTRL Description The clock control register handels clock settings in the CC2538. The settings in CLOCK_CTRL do not always reflect the current chip status which is found in CLOCK_STA register. Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 202 1: A change of system clock source has been initiated and is not finished. Same as when OSC bit in CLOCK_STA and CLOCK_CTRL register are not equal SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 203 0: Clock for GPT2 is gated. 1: Clock for GPT2 is enabled. GPT1 0: Clock for GPT1 is gated. 1: Clock for GPT1 is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 204 0: Clock for GPT1 is gated. 1: Clock for GPT1 is enabled. GPT0 0: Clock for GPT0 is gated. 1: Clock for GPT0 is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 205 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 206 0: SSI1 module is not reset 1: SSI1 module is reset SSI0 0: SSI0 module is not reset 1: SSI0 module is reset SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 207 Reset 31:2 RESERVED This bit field is reserved. 0x0000 0000 UART1 0: Clock for UART1 is gated. 1: Clock for UART1 is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 208 Reset 31:1 RESERVED This bit field is reserved. 0x0000 0000 I2C0 0: Clock for I2C0 is gated. 1: Clock for I2C0 is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 209 0: Clock for AES is gated. 1: Clock for AES is enabled. 0: Clock for PKA is gated. 1: Clock for PKA is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 210 0x0000 0000 0: AES module is not reset 1: AES module is reset 0: PKA module is not reset 1: PKA module is reset SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 211 This bit field is reserved. CRC_REN_RF 1: Enable reset of chip if CRC fails. 0: Disable reset feature of chip due to CRC. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 212 This bit field is reserved. 0x00 0: CLD is disabled. 1: CLD is enabled. Writing to this register shall be ignored if VALID = 0 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 213 This bit field is reserved. 0x0000 0000 ALTMAP 1: Select alternate interrupt map. 0: Select regular interrupt map. (See the ASD document for details.) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 214 RESERVED This bit field is reserved. 0x0000 0000 RFC0 0: Clock for RF CORE is gated. 1: Clock for RF CORE is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 215 0 --> Does not override any power mode settings from SYSREGS and does not prohibit system to go into any power down modes. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 216 0 --> Does not override any power mode settings from SYSREGS and does not prohibit system to go into any power down modes. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 217: Internal Memory
Flash Page Erase ......Flash Lock Bit Page and Customer Configuration Area (CCA) .................... Flash Mass Erase ..................... ROM Sub System ......................SRAM SWRU319B – April 2012 – Revised April 2013 Internal Memory Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 218: Introduction
Introduction The CC2538 family contains flash memory up to 512 kB for storage of program code. The flash memory is programmable from the user software and through the debug interface. The flash controller handles writing and erasing the embedded flash memory. The embedded flash memory consists of up to 256 pages of 2048 bytes each.
Page 219: Example Write Sequence
1 are ignored. Only the bits written 0 are set to 0, whereas all bits FFFFFFF written 1 are ignored. SWRU319B – April 2012 – Revised April 2013 Internal Memory Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 220: Dma Flash Write
DMA channel is configured and how a DMA transfer is initiated to write a block of data from a location in SRAM to flash memory. Internal Memory SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 221: Flash Write Using Dma
To write to the flash using the CPU, a program executing from SRAM must implement the steps outlined in the procedure described in Section 8.3.1. Disable interrupts to ensure the operation does not time out. SWRU319B – April 2012 – Revised April 2013 Internal Memory Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 222: Flash Size Configuration
The following code example of how to erase one flash page in the CC2538 is given for use with the IAR compiler: unsigned char erase_page_num = 3;...
Page 223: Upper 32 Bytes Of Lock Bit Page And Cca Layout
Back door configuration 2006 Reserved Reserved for future use 2005 Reserved Reserved for future use 2004 Reserved Reserved for future use SWRU319B – April 2012 – Revised April 2013 Internal Memory Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 224: Fields At Por/ Reset
0 - Backdoor and boot loader disable Level Sets active level for selected pin on pad A 1 - Active High 0 - Active Low 224 Internal Memory SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 225: Layout Of Byte 2007
NOTE: If the Enable bit is set to 0 in the CCA area of the Lock Bit page, the CC2538 ROM boot loader ignores any received boot loader commands, even if no application image is present in the flash memory.
Page 226: Icepick Tap State
This reflects the command issued to the flash controller for the mass erase 1 - Command issued 0 - Command is not issued 226 Internal Memory SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 227: Rom Sub System
Data can also be transferred to and from the SRAM using the micro direct memory access controller (μDMA). The internal SRAM of the CC2538 is located at 0x2000 0000 of the device memory map, and has the following features: •...
Page 228: Flash_Ctrl Register Summary
0x400D 3014 FLASH_CTRL_DIE CFG0 0x0000 0000 0x18 0x400D 3018 FLASH_CTRL_DIE CFG1 0x0000 2000 0x1C 0x400D 301C FLASH_CTRL_DIE CFG2 8.9.1.1.2 FLASH_CTRL Register Descriptions Internal Memory SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 229 FCTL.BUSY is 1. If FCTL.ERASE is set simultaneously with this bit, the erase operation is started first, then the write is started. SWRU319B – April 2012 – Revised April 2013 Internal Memory Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 230 1 to the FCTL.WRITE bit. New 32-bit data is written only if FCTL.FULL = 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 231 Description These settings are a function of the FLASH information page bit settings, which are programmed during production test, and are subject for specific configuration for multiple device flavors of cc2538. Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 232 These settings are a function of the FLASH information page bit settings, which are programmed during production test, and are subject for specific configuration for multiple device flavors of cc2538. The DIE_*_REVISION registers are an exeception to this, as they are hardwired and are not part of the FLASH information page.
Page 233 Public Version SRAM www.ti.com Bits Field Name Description Type Reset PKA_EN 1: PKA is enabled. 0: PKA is permanently disabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 234: General-Purpose Inputs/Outputs
This chapter describes the input/output (I/O) control and the general-purpose inputs/outputs (GPIOs)..........................Topic Page ...................... I/O Control ......................GPIO ................. I/O Control and GPIO Registers General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 235: Pheripheral Signal Select Values (Same For All Ioc_Pxx_Sel Registers)
SSI1 FSS OUT SSI1 TX_SER OUT I2C SDA I2C SCL GPT0CP1 GPT0CP2 GPT1CP1 0x10 GPT1CP2 0x11 GPT2CP1 0x12 GPT2CP2 0x13 GPT3CP1 0x14 GPT3CP2 SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 236: Gpio
GPIO pins can function as I/O signals for the on-chip peripheral modules. For information on how to setup GPIO pins to be used for alternate hardware (i.e., peripheral) functions, see Section 9.2.2.3. General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 237: Digital I/O Pads (The Diagram Shows One Of 32 Possible I/O Pins)
The data control register is only valid when the AF register selects GPIO not the alternate function. SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 238: Gpiodata Write Example
GPIO Interrupt Both Edges (GPIO_IBE) register • GPIO Interrupt Event (GPIO_IEV) register Interrupts are enabled and disabled through the GPIO Interrupt Enable (GPIO_IE) register. General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 239: Power-Up Interrupt
GPIO_AFSEL register, then it is first necessary to unlock the commit register, as described above, and write the desired protection bits. SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 240: Pad Configuration Override Registers
On reset all bits in the IOC_Pxx_OVER registers are set to 0, except for the PUE bits. This means that at reset all GPIO pads are set as inputs and are pulled up. General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 241: Configuration
This section provides information on the GPIO module instance within this product. Each of the registers within the Module Instance is described separately below. SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 242: Gpio Common Registers Mapping Summary
0x400D 9524 GPIO_GPIOCR 0x0000 0000 0x700 0x400D 9700 GPIO_PMUX 0x0000 0000 0x704 0x400D 9704 GPIO_P_EDGE_CT 0x0000 0000 0x708 0x400D 9708 GPIO_USB_CTRL 242 General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 243: Gpio Register Summary
Table 9-5. GPIO Register Summary Register Name Type Register Width Register Reset Address Offset Physical Address (Bits) 0x0000 0000 0x000 0x400D B000 GPIO_DATA SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 244: Gpio Register Summary
0x400D C420 GPIO_AFSEL 0x0000 0001 0x520 0x400D C520 GPIO_GPIOLOCK 0x0000 00FF 0x524 0x400D C524 GPIO_GPIOCR 0x0000 0000 0x700 0x400D C700 GPIO_PMUX 244 General-Purpose Inputs/Outputs SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 245: Gpio Common Register Descriptions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 General-Purpose Inputs/Outputs Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 246 Bits set: Both edges on corresponding pin trigger an interrupt 0x00 Bits cleared: Interrupt generation event is controlled by GPIOIEV Single edge: Determined by corresponding bit in GPIOIEV register SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 247 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 248 This bit field is reserved. 0x00 0000 Bit written as 1: Clears edge detection logic 0x00 Bit written as 0: Has no effect SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 249 Bits Field Name Description Type Reset 31:0 LOCK A read of this register returns the following values: 0x0000 0001 Locked: 0x00000001 Unlocked: 0x00000000 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 250 The pullup or pulldown is disabled and the direction is set to output for this pin. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 251 Port D bit 1 interrupt request condition: 0: Rising 1: Falling edge PDIRC0 Port D bit 0 interrupt request condition: 0: Rising 1: Falling edge SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 252 Port A bit 5 interrupt request condition: 0: Rising 1: Falling edge PAIRC4 Port A bit 4 interrupt request condition: 0: Rising 1: Falling edge SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 253 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 254 2: Disabled PBIEN5 Port B bit 5 interrupt enable: 1: Enabled 2: Disabled PBIEN4 Port B bit 4 interrupt enable: 1: Enabled 2: Disabled SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 255 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 256 Port B bit 4 masked interrupt status: 1: Detected 0: Not detected PBIACK3 Port B bit 3 masked interrupt status: 1: Detected 0: Not detected SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 257 Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 NOTUSED 0x00 USBACK USB masked interrupt status: 1: Detected 0: Not detected SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 258 Port C bit 2 unmasked interrupt status: 1: Detected 0: Undetected PCIACK1 Port C bit 1 unmasked interrupt status: 1: Detected 0: Undetected SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 259: Ioc Registers
This section provides information on the IOC module instance within this product. Each of the registers within the module instance is described separately below. Register fields should be considered static unless otherwise noted as dynamic. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 260: Ioc Register Summary
0x0000 0004 0x090 0x400D 4090 IOC_PA4_OVER 0x0000 0004 0x094 0x400D 4094 IOC_PA5_OVER 0x0000 0004 0x098 0x400D 4098 IOC_PA6_OVER 0x0000 0004 0x09C 0x400D 409C IOC_PA7_OVER SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 261 0x0000 0000 0x118 0x400D 4118 IOC_CLK_SSIIN_S 0x0000 0000 0x11C 0x400D 411C IOC_CLK_SSI_SSI 0x0000 0000 0x120 0x400D 4120 IOC_SSIRXD_SSI1 0x0000 0000 0x124 0x400D 4124 IOC_SSIFSSIN_SSI SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 262: Ioc Register Descriptions
Field Name Description Type Reset 31:5 RESERVED This bit field is reserved. 0x000 0000 PA1_SEL Select one peripheral signal output for PA1. 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 263 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PA5_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 264 Field Name Description Type Reset 31:5 RESERVED This bit field is reserved. 0x000 0000 PB0_SEL Select one peripheral signal output for PB0. 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 265 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PB4_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 266 Field Name Description Type Reset 31:5 RESERVED This bit field is reserved. 0x000 0000 PB7_SEL Select one peripheral signal output for PB7. 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 267 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PC3_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 268 Field Name Description Type Reset 31:5 RESERVED This bit field is reserved. 0x000 0000 PC6_SEL Select one peripheral signal output for PC6. 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 269 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PD2_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 270 Field Name Description Type Reset 31:5 RESERVED This bit field is reserved. 0x000 0000 PD5_SEL Select one peripheral signal output for PD5. 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 271 0x000 0000 PA0_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 272 0x000 0000 PA3_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 273 0x000 0000 PA6_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 274 0x000 0000 PB1_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 275 0x000 0000 PB4_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 276 0x000 0000 PB7_OVER 0x8: oe - output enable 0x4: pue - pullup enable 0x2: pde - pulldown enable 0x1: ana - analog enable SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 277 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 278 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PC5_OVER SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 279 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PD0_OVER SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 280 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PD3_OVER SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 281 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED PD6_OVER SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 282 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 283 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 284 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 285 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 286 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 287 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 288 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INPUT_SEL SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 289 This bit field is reserved. 0x000 0000 INPUT_SEL 0: PA0 selected as GPT3OCP2 0x00 1: PA1 selected as GPT3OCP2 31: PD7 selected as GPT3OCP2 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 290: Micro Direct Memory Access
10.1 μDMA Introduction ....................10.2 Block Diagram ..................10.3 Functional Description ................10.4 Initialization and Configuration ....................10.5 µDMA Registers Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 291: Μdma Introduction
10.1 μDMA Introduction The CC2538 microcontroller includes a direct memory access (DMA) controller, known as micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the Cortex™-M3 processor, allowing for more efficient use of the processor and the available bus bandwidth. The μDMA controller can perform transfers between memory and peripherals.
Page 292: Μdma Block Diagram
DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. Since the CC2538 uses an AHB matrix, as long as the CPU and μDMA controller are targeting different slaves, the transfers will be concurrent. The only time the CPU will delay a μDMA transfer is if they are targeting the same slave device.
Page 293: Μdma Channel Assignments
SSI1 RX ADC Ch4 softwarere software software Available for Available for Available for SSI1 TX ADC Ch5 software software software SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 294: Priority
If both are asserted, and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. See Table 10-2, which lists how each peripheral supports the two request types. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 295: Request Type Support
Table 10-3. Control Structure Memory Map Offset Channel 0, Primary 0x10 1, Primary SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 296: Channel Control Structure
At the end of a transfer, the μDMA controller updates the control word to set the mode to stop. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 297: Basic Mode
Figure 10-2 shows an example operation in ping-pong mode. SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 298: Example Of Ping-Pong Μdma Transaction
μDMA operation could be used to selectively read the payload of several stored packets of a communication protocol and store them together in sequence in a memory buffer. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 299 B operation with the alternate control structure. The process is repeated for task C. SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 300: Memory Scatter-Gather, Setup And Configuration
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. Figure 10-3. Memory Scatter-Gather, Setup and Configuration Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 301: Memory Scatter-Gather, Μdma Copy Sequence
µDMA controller copies data from source buffer C to alternate control structure of the channel. destination buffer. Figure 10-4. Memory Scatter-Gather, μDMA Copy Sequence SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 302: Peripheral Scatter-Gather
B operation with the alternate control structure. The process is repeated for task C. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 303: Peripheral Scatter-Gather, Setup And Configuration
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the alternate control structure, where it is executed by the µDMA controller. Figure 10-5. Peripheral Scatter-Gather, Setup and Configuration SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 304: Peripheral Scatter-Gather, Μdma Copy Sequence
µDMA controller copies data from source buffer C to alternate control structure of the channel. the peripheral data register. Figure 10-6. Peripheral Scatter-Gather, μDMA Copy Sequence Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 305: Μdma Read Example: 8-Bit Peripheral
Any channel may be used for software requests as long as the corresponding peripheral is not using μDMA for data transfer. SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 306: Μdma Interrupt Assignments
2. Set bit 30 of the DMA Channel Primary Alternate Clear (UDMA_ALTCLR) register to select the primary channel control structure for this transfer. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 307: Channel Control Structure Offsets For Channel
XFERMODE field of the channel control word at offset 0x1E8. This field is automatically cleared at the end of the transfer. SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 308: Channel Control Structure Offsets For Channel
Arbitrates after 4 transfers XFERSIZE 13:4 Transfer 64 items NXTUSEBURST N/A for this transfer type XFERMODE Use basic transfer mode Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 309: Start The Transfer
Control table base + 0x080 Channel 8 primary source end pointer Control table base + 0x084 Channel 8 primary destination end pointer SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 310: Primary And Alternate Channel Control Structure Offsets For Channel 8
However, ping-pong mode can be configured without interrupts by polling. The interrupt handler is triggered after each buffer completes. Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 311: Udma Register Summary
Register Reset Address Offset Physical Address (Bits) 0x001F 0000 0x000 0x400F F000 UDMA_STAT 0x0000 0000 0x004 0x400F F004 UDMA_CFG SWRU319B – April 2012 – Revised April 2013 Micro Direct Memory Access Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 312: Udma Register Descriptions
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED DMACHANS RESERVED STATE Micro Direct Memory Access SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 313 31:1 RESERVED This bit field is reserved. 0x0000 0000 MASTEN Controller master enable 0: Disables the uDMA controller. 1: Enables the uDMA controller. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 314 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 WAITREQ SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 315 Bit 0 corresponds to channel 0. This bit is automatically cleared as described above. A bit can also be manually cleared by setting the corresponding CLR[n] bit in the DMAUSEBURSTCLR register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 316 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 317 DMAENASET register meaning that channel [n] is disabled for uDMA transfers. Note: The controller disables a channel when it completes the uDMA cycle. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 318 Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 319 0: No bus error is pending 1: A bus error is pending This bit is cleared by writing 1 to it. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 320 See section titled "Channel Assignments" in Micro Direct Memory Access chapter. 23:20 CH5SEL uDMA channel 5 source select See section titled "Channel Assignments" in Micro Direct Memory Access chapter. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 321 See section titled "Channel Assignments" in Micro Direct Memory Access chapter. CH8SEL uDMA channel 8 source select See section titled "Channel Assignments" in Micro Direct Memory Access chapter. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 322 See section titled "Channel Assignments" in Micro Direct Memory Access chapter. 23:20 CH29SEL uDMA channel 29 source select See section titled "Channel Assignments" in Micro Direct Memory Access chapter. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 323 See section titled "Channel Assignments" in Micro Direct Memory Access chapter. CH24SEL uDMA channel 24 source select See section titled "Channel Assignments" in Micro Direct Memory Access chapter. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 324: General-Purpose Timers
This chapter describes the general-purpose timers..........................Topic Page ................... 11.1 General-Purpose Timers ....................11.2 Block Diagram ..................11.3 Functional Description ..............11.4 General-Purpose Timer Registers General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 325: Gptm Module Block Diagram
16-bit timers (referred to as timer A and timer B) that can be configured to operate independently as timers, or concatenated to operate as one 32-bit timer. The GPT is one timing resource available on the CC2538 microcontroller. Other timer resources include the System Timer (SysTick) (see Section 3.2.1), MAC timer, sleep timer and watchdog timer, see the...
Page 326: General-Purpose Timer Capabilities
The GPTM Timer A Prescale Value (GPTIMER_TAPV) register (see GPTIMER_TAPV) and the GPTM Timer B Prescale Value (GPTIMER_TBPV) register (see GPTIMER_TBPV). General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 327: Timer Modes
If the TnSTALL bit in the GPTIMER_CTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 328: Counter Values When The Timer Is Enabled In Input Edge-Count Mode
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 329: Input Edge-Count Mode Example, Counting Down
Table 11-4. Counter Values When the Timer is Enabled in Input Event-Count Mode Register Count Down Mode CountUp Mode GPTIMER_TnR GPTM_TnILR GPTIMER_TnV GPTM_TnILR GPTIMER_TnPV GPTM_TnPR SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 330: Input Edge-Time Mode Example
0x1, the TnCMR bit to 0x0, and the TnMR field to 0x1 or 0x2. Table 11-5 shows the values that are loaded into the timer registers when the timer is enabled. General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 331: Counter Values When The Timer Is Enabled In Pwm Mode
50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTIMER_TnILR=0xC350 and the match value is GPTIMER_TnMATCHR=0x411A. SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 332: Bit Pwm Mode Example
GPTIMER_TnMATCHR value is the same as the GPTIMER_TnILR value. In this situation, if the PLO bit is 0, the CCP signal goes high when the GPTIMER_TnILR value is loaded and the match would be essentially ignored. General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 333: Wait-For-Trigger Mode
Care must be taken that the TAWOT bit is never set in GPTM0. Figure 11-8 shows how the GPTMCFG bit affects the daisy-chain. This function is valid for one-shot, periodic, and PWM modes. SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 334: Timer Daisy-Chain
GPTIMER_TBR • GPTM Timer A Value (GPTIMER_TAV) register [15:0], see GPTIMER_TAV • GPTM Timer B Value (GPTIMER_TBV) register [15:0], see GPTIMER_TBV General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 335: Initialization And Configuration
6. Load the timer start value into the GPTM Timer n Interval Load (GPTIMER_TnILR) register. 7. Load the event count into the GPTM Timer n Match (GPTIMER_TnMATCHR) register. SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 336: Input Edge_Timing Mode
GPTMTnILR register, and the change takes effect at the next cycle after the write. General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 337: Gptimer Common Registers Mapping Summary
0x0000 0000 0x064 GPTIMER_TBPV 0x0000 0000 0x068 GPTIMER_PP 0x0000 0000 0xFC0 11.4.1.1.2 GPTIMER Instances Register Mapping Summary 11.4.1.1.2.1 GPTIMER0 Register Summary SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 338: Gptimer Register Summary
0x4003 100C GPTIMER_CTL 0x0000 0000 0x010 0x4003 1010 GPTIMER_SYNC 0x0000 0000 0x018 0x4003 1018 GPTIMER_IMR 0x0000 0000 0x01C 0x4003 101C GPTIMER_RIS 338 General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 339: Gptimer Register Summary
0x4003 2024 GPTIMER_ICR 0xFFFF FFFF 0x028 0x4003 2028 GPTIMER_TAILR 0x0000 FFFF 0x02C 0x4003 202C GPTIMER_TBILR 0xFFFF FFFF 0x030 0x4003 2030 GPTIMER_TAMAT SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 340 0x4003 303C GPTIMER_TBPR 0x0000 0000 0x040 0x4003 3040 GPTIMER_TAPMR 0x0000 0000 0x044 0x4003 3044 GPTIMER_TBPMR 0xFFFF FFFF 0x048 0x4003 3048 GPTIMER_TAR 340 General-Purpose Timers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 341: Gptimer Common Register Descriptions
0x2: Reserved 0x3: Reserved 0x4: 16-bit timer configuration. The function is controlled by bits [1:0] of GPTMTAMR and GPTMTBMR. 0x5-0x7: Reserved SWRU319B – April 2012 – Revised April 2013 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 342 0: The match interrupt is disabled. 1: An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 343 This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output. 0: Interrupt is disabled. 1: Interrupt is enabled. This bit is valid only in PWM mode. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 344 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 345 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 346 1: Interrupt is enabled. TBTOIM GPTM Timer B time-out interrupt mask 0: Interrupt is disabled. 1: Interrupt is enabled. RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 347 CAERIS GPTM Timer A capture event raw interrupt CAMRIS GPTM Timer A capture match raw interrupt TATORIS GPTM Timer A time-out raw interrupt SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 348 This bit field is reserved. 0x0000 WUECINT GPTM write update error interrupt clear 15:12 RESERVED This bit field is reserved. TBMCINT GPTM Timer B match interrupt clear SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 349 TBILR Bits Field Name Description Type Reset 31:16 RESERVED This bit field is reserved. 0x0000 15:0 TBILR GPTM B interval load register 0xFFFF SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 350 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED TAPSR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 351 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED TBPSR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 352 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Bits Field Name Description Type Reset 31:16 RESERVED This bit field is reserved. 0x0000 15:0 GPTM Timer B register 0xFFFF SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 353 31:24 RESERVED This bit field is reserved. 0x00 23:16 GPTM Timer B prescale register (16-bit mode) 0x00 15:0 GPTM Timer B register 0xFFFF SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 354 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Bits Field Name Description Type Reset 31:16 RESERVED This bit field is reserved. 0x0000 15:0 GPTM Timer A prescaler value 0x0000 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 355 0: Timer A and Timer B are 16 bits wide with 8-bit prescale. 1: Timer A and Timer B are 32 bits wide with 16-bit prescale. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 356: Mac Timer
CC2538 devices • For general radio timekeeping when running the radio in proprietary mode on the CC2538 device When the MAC timer is used with the sleep timer, the timing function is provided even when the system enters low-power modes PM1 and PM2. The timer runs at a speed according to the system clock. If the MAC timer is to be used with the sleep timer, the system clock source must be the 32-MHz crystal whenever the MAC timer is running, and an external 32-kHz XOSC should be used for accurate results.
Page 357: Timer Operation
MACTIMER_COMPARE1M bit in the RFCORE_SFR_MTIRQM register or the MACTIMER_COMPARE2M bit in the RFCORE_SFR_MTIRQM register is set to 1. SWRU319B – April 2012 – Revised April 2013 MAC Timer Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 358: Overflow Count
RFCORE_SFR_MTMOVF0 if the MTMOVFSEL bit in the RFCORE_SFR_MTMSEL register is set to 001. 12.2 Interrupts The timer has six individually maskable interrupt sources. These are the following: MAC Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 359: Event Outputs (Dma Trigger And Radio Events)
The MAC timer has two event outputs, MT_EVENT1 and MT_EVENMT. These can be used as DMA triggers, as inputs to the radio, for conditions in conditional instructions in the CSP on CC2538, or for timing TX or RX in CC2538 when running the radio in proprietary mode. The event outputs can be configured individually to any of the following events: •...
Page 360: Timer Synchronous Start
Because the MAC timer and sleep timer clocks are asynchronous with a noninteger clock ratio, there is a maximum error of ±1 in the calculated timer value compared to the ideal timer value, not considering clock inaccuracies. MAC Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 361: Mac Timer Registers
0x00 0x4008 8800 RFCORE_SFR_MTCTRL 0x0000 0002 0x04 0x4008 8804 RFCORE_SFR_MTIRQM 0x0000 0000 0x08 0x4008 8808 RFCORE_SFR_MTIRQF 0x0000 0000 0x0C 0x4008 880C SWRU319B – April 2012 – Revised April 2013 MAC Timer Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 362: Rfcore_Sfr Register Descriptions
MACTIMER_EVENT1_ Selects the event that triggers an MT_EVENT1 pulse 000: MT_per_event 001: MT_cmp1_event 010: MT_cmp2_event 011: MTovf_per_event 100: MTovf_cmp1_event 101: MTovf_cmp2_event 110: Reserved 111: No event MAC Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 363 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 364 MACTIMER_COMPAR Set when the MAC Timer counter counts to the value set at MT_cmp1 MACTIMER_PERF Set when the MAC Timer counter would have counted to a value equal to MT_per, but instead wraps to 0 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 365 When reading the MTM0 register with MTMSEL.MTMSEL set to 000 and MTCTRL.LATCH_MODE set to 1, the timer (MTtim) and overflow counter (MTovf) values are latched. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 366 Indirectly returns and modifies bits [15:8] of an internal register, 0x00 depending on the value of MTMSEL.MTMSEL. Reading this register with MTMSEL.MTMOVFSEL set to 000 returns the latched value of MTovf[15:8]. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 367 (MTovf) is latched. When reading the MTM0 register with MTMSEL.MTMOVFSEL set to 000 and MTCTRL.LATCH_MODE set to 1, the overflow counter value (MTovf) is latched. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 368: Sleep Timer
Section 11.3.2.2.4) ........................... Topic Page ......................13.1 General ....................13.2 Timer Compare ....................13.3 Timer Capture ..................13.4 Sleep Timer Registers Sleep Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 369: General
Failure to follow the procedure may cause the capture functionality to stop working until a chip reset. SWRU319B – April 2012 – Revised April 2013 Sleep Timer Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 370: Sleep Timer Capture
This section provides information on the SMWDTHROSC module instance within this product. Each of the registers within the module instance is described separately below. Register fields should be considered static unless otherwise noted as dynamic. Sleep Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 371: Smwdthrosc Register Summary
[7:0] of the Sleep Timer count. When writing this register sets the low bits [7:0] of the compare value. SWRU319B – April 2012 – Revised April 2013 Sleep Timer Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 372 The value read is latched at the time of reading register ST0. The value written is latched when ST0 is written. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 373 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 374 Field Name Description Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 STCV2 Bits [23:16] of Sleep Timer capture value 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 375 Field Name Description Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 STCV3 Bits [32:24] of Sleep Timer capture value 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 376: Watchdog Timer
The contents of the 15-bit counter are retained during all power modes, and the WDT continues counting when entering active mode again..........................Topic Page ....................14.1 Watchdog Timer ................14.2 Watchdog Timer Registers Watchdog Timer SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 377: Smwdthrosc Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Watchdog Timer Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 378 00: Twdt x 32768 01: Twdt x 8192 10: Twdt x 512 11: Twdt x 64 Writing these bits when EN = 1 has no effect. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 379 (DMA). Several modes of operation are available..........................Topic Page ..................... 15.1 ADC Introduction ....................15.2 ADC Operation ..............15.3 Analog-to-Digital Converter Registers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 380: Adc Block Diagram
The reference in this case must not depend on the battery voltage; for instance, the AVDD5 voltage is not a valid reference. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 381: Adc Conversion Sequences
The last channel of a sequence is selected with the SCH bits in the SOC_ADC_ADCCON2 register as described previously (see Section 15.2.2, ADC Conversion Sequences. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 382: Adc Conversion Results
DMA status registers. See Chapter 10 for details on DMA. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 383: Analog-To-Digital Converter Registers
Selects the event that starts a new conversion sequence 00: Not implemented 01: Full speed. Do not wait for triggers 10: Timer 1 channel 0 compare event 11: ADCCON1.ST = 1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 384 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN0-AIN1 1001: AIN2-AIN3 1010: AIN4-AIN5 1011: AIN6-AIN7 1100: GND 1101: Reserved 1110: Temperature sensor 1111: VDD/3 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 385 Description Type Reset 31:8 RESERVED This bit field is reserved. Least-significant part of ADC conversion result 0x00 RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 386 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Bits Field Name Description Type Reset 31:8 RESERVED This bit field is reserved. Most-significant part of ADC conversion result 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 387: Random Number Generator
This chapter provides more information about the random number generator (RNG) and its usage..........................Topic Page ....................16.1 Introduction ............... 16.2 Random-Number-Generator Operation ..............16.3 Random Number Generator Registers SWRU319B – April 2012 – Revised April 2013 Random Number Generator Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 388: Basic Structure Of The Rng
SOC_ADC_RNDL register. For the CC2538, when a random value is required, writing the SOC_ADC_RNDL register with random bits from the IF_ADC in the RF receive path seeds the LFSR. To use this seeding method, first power on the radio.
Page 389: Crc16
Read as 1 until conversion completes 0: No conversion in progress. 1: Start a conversion sequence if ADCCON1.STSEL = 11 and no sequence is running. SWRU319B – April 2012 – Revised April 2013 Random Number Generator Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 390 8 MSBs of the random number. When used for CRC calculations, reading this register returns the 8 MSBs of the CRC result. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 391: Analog Comparator
Public Version Chapter 17 SWRU319B – April 2012 – Revised April 2013 Analog Comparator The analog comparator in the CC2538 device has the following features: • Low-power operation • Wake-up source ........................... Topic Page ....................17.1 Introduction ................17.2 Analog Comparator Registers SWRU319B –...
Page 392: Analog Comparator
This section provides information on the SOC_ADC module instance within this product. Each register within the module instance is described separately below. Analog Comparator SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 393: Soc_Adc Register Summary
Description Type Reset 31:8 RESERVED This bit field is reserved. RESERVED This bit field is reserved. Comparator enable OUTPUT Comparator output SWRU319B – April 2012 – Revised April 2013 Analog Comparator Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 394: Universal Asynchronous Receivers And Transmitters
18.2 Block Diagram ................... 18.3 Signal Description ..................18.4 Functional Description ................18.5 Initialization and Configuration ....................18.6 UART Registers Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 395: Universal Asynchronous Receivers And Transmitters
Universal Asynchronous Receivers and Transmitters www.ti.com 18.1 Universal Asynchronous Receivers and Transmitters The CC2538 controller includes two UARTs with the following features: • Programmable baud-rate generator allowing speeds up to 2 Mbps for regular speed (divide by 16) and 4 Mbps for high speed (divide by 8) •...
Page 396: Uart Module Block Diagram
I = Input; O = Output; I/O = Bidrectional TTL indicates the pin has TTL-compatible voltage levels. 396 Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 397: Uart Character Frame
Each CC2538 UART performs the functions of parallel-to-serial and serial-to-parallel conversions. The CC2538 UART is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive through the TXE and RXE bits of the UART Control (UART_CTL) register (see UART_CTL).
Page 398: Data Transmission
Clear-To-Send input on the receiving device, and connecting the Request-To-Send output on the receiving device to the U1CTS input. Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 399: Lin Message
SWRU319B – April 2012 – Revised April 2013 Universal Asynchronous Receivers and Transmitters Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 400: Lin Synchronization Field
UART_RSR register shows overrun status through the OE bit. If the FIFOs are disabled, the empty and full flags are set according to the status of the 1-byte-deep holding registers. Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 401: Interrupts
5. For more information on pin connections, see Section 9.1.1, I/O Muxing, of Chapter 9, General Purpose Input/Outputs (GPIO). SWRU319B – April 2012 – Revised April 2013 Universal Asynchronous Receivers and Transmitters Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 402: Uart Common Registers Mapping Summary
0x004 UART_ECR 0x0000 0000 0x004 UART_FR 0x0000 0090 0x018 UART_ILPR 0x0000 0000 0x020 UART_IBRD 0x0000 0000 0x024 402 Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 403: Uart Register Summary
0x0000 0000 0x094 0x4000 C094 UART_LSS 0x0000 0000 0x098 0x4000 C098 UART_LTIM 0x0000 0000 0x0A4 0x4000 C0A4 UART_NINEBITAD SWRU319B – April 2012 – Revised April 2013 Universal Asynchronous Receivers and Transmitters Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 404: Uart Register Summary
UART_NINEBITAM 0x0000 0003 0xFC0 0x4000 DFC0 UART_PP 0x0000 0000 0xFC8 0x4000 DFC8 UART_CC 18.6.1.2 UART Common Register Descriptions Universal Asynchronous Receivers and Transmitters SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 405 Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART. SWRU319B – April 2012 – Revised April 2013 Universal Asynchronous Receivers and Transmitters Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 406 This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 407 1: If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full. 0: The transmitter is not full. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 408 Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 ILPDVSR IrDA low-power divisor 0x00 This field contains the 8-bit low-power divisor value. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 409 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED WLEN SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 410 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 411 0: The UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 412 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 413 UARTRIS register is set. 0: The RXRIS interrupt is suppressed and not sent to the interrupt controller. RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 414 1: A framing error has occurred. 0: No interrupt This bit is cleared by writing 1 to the FEIC bit in the UARTICR register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 415 0: An interrupt has not occurred or is masked. This bit is cleared by writing 1 to the LMSBIC bit in the UARTICR register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 416 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 417 1: μDMA receive requests are automatically disabled when a receive error occurs. 0: μDMA receive requests are unaffected when a receive error occurs. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 418 0x0000 This field contains the value of the free-running timer when either the sync edge 5 or the sync edge 1 was detected. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 419 This bit field is reserved. 0x00 ADDR Self address for 9-bit mode 0x00 This field contains the address that should be matched when UART9BITAMASK is 0xFF. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 420 0: The UART module does not provide support for the transmission of 9-bit data for RS-485 support. RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 421 PIOSC setting above. 0: The UART system clock is determined by the SYS DIV setting in the system controller. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 422: Synchronous Serial Interface
19.3 Signal Description ..................19.4 Functional Description ....................19.5 DMA Operation ................19.6 Initialization and Configuration ....................19.7 SSI Registers Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 423: Ssi Module Block Diagram
19.1 Synchronous Serial Interface The CC2538 microcontroller includes two SSI modules. Each SSI is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments SSIs. The CC2538 SSI modules have the following features: •...
Page 424: Signals For Ssi (64Lqfp)
FIFO by writing the SSI Data (SSI_DR) register (see SSI_DR), and data is stored in the FIFO until it is read out by the transmission logic. Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 425: Receive Fifo
(MSB). Three basic frame types can be selected: • Texas Instruments synchronous serial • Freescale SPI SWRU319B – April 2012 – Revised April 2013 Synchronous Serial Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 426: Ti Synchronous Serial Frame Format (Single Transfer)
(pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, before the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk and latch data from the other device on the falling edge.
Page 427: Freescale Spi Format (Single Transfer) With Spo = 0 And Sph
In the case of a single-word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle high state one SSIClk period after the last bit is captured. SWRU319B – April 2012 – Revised April 2013 Synchronous Serial Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 428: Freescale Spi Frame Format With Spo = 0 And Sph
Note: Q is undefined. Figure 19-7. Freescale SPI Frame Format (Single Transfer) With SPO = 1 and SPH = 0 Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 429: Freescale Spi Frame Format (Continuous Transfer) With Spo = 1 And Sph
When the SSI is configured as a master, it enables the SSIClk pad. • When the SSI is configured as a slave, it disables the SSIClk pad. SWRU319B – April 2012 – Revised April 2013 Synchronous Serial Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 430: Microwire Frame Format (Single Frame)
The off-chip slave device can 3-state the receive line either on the falling edge of NOTE: SSIClk after the LSB has been latched by the receive shifter or when the SSIFss pin goes High. Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 431: Microwire Frame Format (Continuous Transfer)
For more details about programming the μDMA controller, see Chapter 19.6 Initialization and Configuration To enable and initialize the SSI, perform the following steps: SWRU319B – April 2012 – Revised April 2013 Synchronous Serial Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 432 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSI_CR1 register. Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 433: Ssi Common Registers Mapping Summary
0x4000 801C SSI_MIS 0x0000 0000 0x020 0x4000 8020 SSI_ICR 0x0000 0000 0x024 0x4000 8024 SSI_DMACTL 0x0000 0000 0xFC8 0x4000 8FC8 SSI_CC SWRU319B – April 2012 – Revised April 2013 Synchronous Serial Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 434: Ssi Register Summary
Reset value: 0x0 00: Motorola SPI frame format 01: TI synchronous serial frame format 10: National Microwire frame format 11: Reserved Synchronous Serial Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 435 0: Normal serial port operation is enabled. 1: The output of the transmit serial shifter is connected to the input of the receive serial shift register internally. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 436 1: Receive FIFO is full. SSI receive FIFO not empty (RO) Reset value: 0x0 0: Receive FIFO is empty. 1: Receive FIFO is not empty. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 437 SSI receive time-out interrupt mask (R/W) Reset value: 0x0 0: RX FIFO time-out interrupt is masked. 1: RX FIFO time-out interrupt is not masked SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 438 This bit field is reserved. 0x000 TXMIS SSI SSITXINTR masked state (RO) Reset value: 0x0 Gives the interrupt state (after masking) of SSITXINTR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 439 1: uDMA for the transmit FIFO is enabled. RXDMAE Receive DMA enable 0: uDMA for the receive FIFO is disabled. 1: uDMA for the receive FIFO is enabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 440 1: The SSI system clock is running on the same clock as the baud clock, as per PIOSC setting above. 0: The SSI system clock is determined by the SYS DIV setting in the system controller. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 441: Inter-Integrated Circuit Interface
20.1 Inter-Integrated Circuit Interface ....................20.2 Block Diagram ..................20.3 Functional Description ................20.4 Initialization and Configuration ....................20.5 I C Registers SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 442: Bus Configuration
LCDs, tone generators, and so on. The I C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The CC2538 device includes one I module, providing the ability to interact (both transmit and receive) with other I C devices on the bus.
Page 443: Start And Stop Conditions
C Bus Functional Overview The I C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on the cc2538 controller. SDA is the bidirectional serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines are high.
Page 444: Complete Data Transfer With A 7-Bit Address
The slave transmitter must then release SDA to allow the master to generate a Stop or a Repeated Start condition. Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 445: Examples Of I
The I C can generate interrupts when the following conditions are observed: • Master transaction completed • Master arbitration lost SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 446: Loopback Operation
20.3.5.1 I C Master Command Sequences Figure 20-7 through Figure 20-12 show the command sequences available for the I C master. Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 447: Master Single Transmit
BUSBSY bit=0? Write ---0-111 to I2CM_CTRL Read I2CM_CTRL BUSY bit=0? Error service ERROR bit=0? Idle Figure 20-7. Master Single TRANSMIT SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 448: Master Single Receive
Write ---00111 to I2CM_CTRL Read I2CM_CTRL BUSY bit=0? Error service ERROR bit=0? Read data from I2CM_DR Idle Figure 20-8. Master Single RECEIVE Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 449: Master Transmit With Repeated Start Condition
Write ---0-101 to I2CM_CTRL Idle Read I2CM_CTRL BUSY bit=0? Error service ERROR bit=0? Idle Figure 20-9. Master TRANSMIT With Repeated Start Condition SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 450: Master Receive With Repeated Start Condition
Read I2CM_CTRL BUSY bit=0? ERROR bit=0? Read data from Error service I2CM_DR Idle Figure 20-10. Master RECEIVE With Repeated Start Condition Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 451: Master Receive With Repeated Start After Transmit With Repeated Start Condition
Master operates in direction master receive mode Idle Figure 20-11. Master RECEIVE With Repeated Start After TRANSMIT With Repeated Start Condition SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 452: Master Transmit With Repeated Start After Receive With Repeated Start Condition
Figure 20-12. Master TRANSMIT With Repeated Start After RECEIVE With Repeated Start Condition 20.3.5.2 I C Slave Command Sequences Figure 20-13 shows the command sequence available for the I C slave. Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 453: Slave Command Sequence
6. Place data (byte) to be transmitted in the data register by writing the I2CM_DR register with the desired data. SWRU319B – April 2012 – Revised April 2013 Inter-Integrated Circuit Interface Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 454: I2Cm Register Summary
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Inter-Integrated Circuit Interface SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 455 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 456 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 457 1: A master interrupt is pending. 0: No interrupt This bit is cleared by writing 1 to the IC bit in the I2CMICR register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 458 31:6 RESERVED This bit field is reserved. 0x000 0000 I2C slave function enable 1: Slave mode is enabled. 0: Slave mode is disabled. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 459: I2Cs Register Summary
Description I2C slave own address This register consists of seven address bits that identify the CC2538 I2C device on the I2C bus. Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 460 31:1 RESERVED This bit field is reserved. 0x0000 0000 Device active 0: Disables the I2C slave operation 1: Enables the I2C slave operation SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 461 DATARIS bit in the I2CSRIS register is set. 0: The DATARIS interrupt is surpressed and not sent to the interrupt controller. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 462 0: An interrupt has not occurred or is masked. This bit is cleared by writing 1 to the STARTIC bit in the I2CSICR register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 463 Writing 1 to this bit clears the DATARIS bit in the I2CSRIS register and the DATAMIS bit in the I2CSMIS register. A read of this register returns no meaningful data. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 464 21.9 EndPoint 0 Interrupts ....................21.10 Endpoints 1–5 ......................21.11 DMA .................... 21.12 Remote Wake-Up ................. 21.13 USB Registers Overview ....................21.14 USB Registers USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 465: Usb Controller Block Diagram
PLLLOCKED bit in the USB_CTRL register (status flag) to go high. When the PLL has locked, it is safe to use the USB controller. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 466: Usb Interrupt Flags And Associated Interrupt-Enable Mask Registers
(typically in a local variable on the stack) and allowing multiple accesses to them. Figure 21-2 is a flow chart for the USB interrupt service routine. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 467: Usb Interrupt Service Routine
USB cable is connected. The USB controller performs the following actions when a USB reset occurs: • Sets the USB_ADDR register to 0. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 468: Usb Index Register
Following subsections look at the sequence of events that the software must perform to process the different types of device request. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 469: Zero Data Requests
USB_CS0.DATAEND has been set, then the USB controller will send a STALL. An Endpoint 0 interrupt will be generated and the USB_CS0.SENTSTALL bit will be set. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 470: Endpoint 0 Interrupts
USB_CS0.SETUPEND bit would be set. In either case, the firmware should abort processing the current control transfer and set the state to IDLE. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 471 Data phase, Endpoint 0 remains in IDLE state to accept the next device request. Figure 21-3 shows the states that Endpoint 0 enters for the different phases of the control transfer. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 472: Endpoint 0 States
Clear OutPktRdy and Set DataEnd Figure 21-3. Endpoint 0 States Figure 21-4 is a flow chart for the Endpoint 0 service routine. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 473: Endpoint 0 Service Routine
IDLE mode IDLE ? State TX mode TX ? State RX mode * By default SWRU310-003 Figure 21-4. Endpoint 0 Service Routine SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 474: Error Conditions
IDLE state. Figure 21-5 is a flow chart for the handling of the SETUP phase of the control transfer. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 475: Setup Phase Of Control Transfer
SWRU310-004 Figure 21-5. SETUP Phase of Control Transfer Figure 21-6 is a flow chart of control transactions in the SETUP phase. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 476: Setup Phase Control Transactions
32, the residual packet is a zero-length data packet, because a packet size less than 32 bytes denotes the end of the transfer. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 477: In Data Phase For Control Transfer
Set InPktRdy Last Packet Set InPktRdy and Set DataEnd State ® IDLE Return SWRU310-005 Figure 21-7. IN Data Phase for Control Transfer SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 478: In Phase Control Transactions
DataEnd if appropriate Status Phase * If enabled CPU should clear SentStall bit SWRU310-008 Figure 21-8. IN Phase Control Transactions USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 479: Control Transactions Following Status Stage (Tx Mode)
32, the residual packet is a zero-length data packet, because a data packet size less than 32 bytes denotes the end of the transfer. NOTE: For isochronous transfers, there is no handshake packet from the device. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 480: Out Data Phase For Control Transfer
FIFO Last Packet CirOutPkRdy CirOutPkRdy and DataEnd State ® IDLE Return SWRU310-006 Figure 21-10. OUT Data Phase for Control Transfer USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 481: Out Phase Control Transactions
CPU should unload FIFO , clear OutPktRdy & set DataEnd as appropriate Status Phase * If enabled SWRU310-010 Figure 21-11. OUT Phase Control Transactions SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 482: Control Transactions Following Status Stage (Rx Mode)
The USB_INDEX register must have the value of the endpoint number before the indexed endpoint registers are accessed. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 483: In/Out Fifos
For isochronous endpoints, double-buffering is required to avoid data underrun (since there can be little time between the isochronous packet in one USB frame and the packet in the next). SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 484: Fifo Access
USB controller responds with a STALL handshake to IN tokens. The USB_CSIL.SENTSTALL bit is set, and an interrupt is generated, if enabled. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 485 ACK was received from the host. Figure 21-14 is a flow chart of Bulk and Interrupt IN transactions. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 486: Bulk And Interrupt In Transactions
CPU needs to reload FIFO , IDLE and set InPktRdy * If enabled SWRU310-012 Figure 21-14. Bulk and Interrupt IN Transactions USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 487: Isochronous In Endpoint
It is up to the application to determine how this error condition is handled. Figure 21-15 is a flow chart of Isochronous IN transactions. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 488: Isochronous In Transactions
USB_CSOH register should be set as shown below : • AUTOCLEAR to 1 if AutoClear feature is required. • ISO to 0 to enable Bulk protocol. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 489 Interrupt OUT endpoint uses almost the same protocol as a Bulk OUT endpoint and can be used the same way. Figure 21-16 is a flow chart of Bulk and Interrupt OUT transactions. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 490: Bulk And Interrupt Out Transactions
USB_CSOL.OVERRUN bit is set and the packet data is lost. Firmware can reduce this possibility by using double-buffering and using DMA to unload data packets effectively. USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 491 It is up to the application to determine how this error condition is handled. Figure 21-17 is a flow chart of Isochronous OUT transactions. SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 492: Isochronous Out Transactions
USB host must grant the device the privilege to perform remote wakeup (through a SET_FEATURE request). USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 493: Usb Register Summary
0x4008 9080 USB_F0 0x0000 0000 0x88 0x4008 9088 USB_F1 0x0000 0000 0x90 0x4008 9090 USB_F2 0x0000 0000 0x98 0x4008 9098 USB_F3 SWRU319B – April 2012 – Revised April 2013 USB Controller Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 494: Usb Register Descriptions
IN token is received before an SOF token, then a zero length data packet will be sent. RESERVED This bit field is reserved. Indicates that reset signaling is present on the bus USB Controller SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 495 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 496 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 497 0: Interrupt disabled 1: Interrupt enabled OUTEP1IE Interrupt enable for OUT endpoint 1 0: Interrupt disabled 1: Interrupt enabled RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 498 0x00 0000 FRAMEL Bits 7:0 of the 11-bit frame number 0x00 The frame number is only updated upon successful reception of SOF tokens SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 499 This bit field is reserved. 0x00 0000 PLLLOCKED PLL lock status. The PLL is locked when USB_CTRL.PLLLOCKED is 1. RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 500 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 501 An interrupt is generated when the bit is cleared. USB_CSIL.PKTPRESENT [RO]: This bit is set when there is at least one packet in the IN endpoint FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 502 RESERVED This bit field is reserved. INDBLBUF IN endpoint FIFO double-buffering enable: 0: Double buffering disabled 1: Double buffering enabled SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 503 FIFO. Firmware should clear this bit. FIFOFULL This bit is set when no more packets can be loaded into the OUT endpoint FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 504 Bits 7:0 of the of the number of bytes received in the packet in the OUT endpoint {1-5} FIFO Valid only when USB_CSOL.OUTPKTRDY is set SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 505 Reading this register unloads one byte from the EP1 OUT FIFO. Writing to this register loads one byte into the EP1 IN FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 506 Reading this register unloads one byte from the EP4 OUT FIFO. Writing to this register loads one byte into the EP4 IN FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 507 Reading this register unloads one byte from the EP5 OUT FIFO. Writing to this register loads one byte into the EP5 IN FIFO. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 508: Security Core
Public Version Chapter 22 SWRU319B – April 2012 – Revised April 2013 Security Core This chapter provides information on configuring the security engine of the CC2538 device..........................Topic Page ....................22.1 PKA Engine ................. 22.2 AES and SHA Cryptoprocessor ..................
Page 509: Pka Engine
Size of a register or signal in bits where n > m [31:0] indicates a size of 32 bits with most significant bit 31 and least significant bit 0. SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 510: Overview
50% of the exponent bits are ‘1’, no use of CRT: straight modular exponentiation using 1024/2048-bit modulus and exponent vectors (timing includes the necessary pre- and post-calculations). 510 Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 511: Summary Of Pkcp Vector Operations
A mod B → C Modulo Dividend Divisor Remainder Compare A = B, A < B, A > B Input1 Input2 SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 512: Restrictions On Input Vectors For Pkcp Operations
Quotient → A_Len – B_Len + 1 Modulo Remainder → B_Len + 1 Compare updates the Compare None PKA_COMPARE register Copy A_Len 512 Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 513: Pkcp Result Vector / Input Vector Overlap Restrictions
B → D length = Modulus, length = B_Len Base, length = B_Len Result & Workspace ACT4 A_Len ExpMod- variable SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 514: Restrictions On Input Vectors For Expmod Operations
32-bit words, i.e. without trailing zero words at the end. If the last word of the modulus vector as given is non-zero, ‘M_Len’ equals B_Len. Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 515: Expmod Result Vector/Scratchpad Area Memory Allocation
Base (PKA_CPTR) vector with the start of the Scratchpad/result (PKA_DPTR) area saves memory space for non-CRT operations and is therefore indicated separately: SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 516: Required Pka Ram Sizes For Exponentiations
Vector D operation NumToInvert, length Modulus,length = ModInv A-1 mod B → D Not used Result & Workspace = A_Len B_Len 516 Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 517: Pka_Shift Result Values For Modinv Operation
φ = (p-1)(q-1) and p and q both primeNote that φ is even. However, since e must be odd (otherwise no inverse exists), d can be calculated as: SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 518: Summary Of Ecc Operations
VectorD result point undefinedOther values are reserved Table 22-19 Table 22-20 list restrictions on the input and result vectors for the ECC operations. Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 519: Operational Restrictions On Input Vectors For Ecc Operations
Scaling to other vector sizes with… (vector lengths in bits) (approximate) 1K + 1K addition Max (A_Len, B_Len) 1K – 1K subtract Max (A_Len, B_Len) SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 520: Exponentiation Performance For 16-Bit Pkcp-Only
+ seq Exp.Mod. 1024 2,244,311 8,977 sign/encr/de sequencer Exp.Mod. 2,299,238 9,197 cr 512 sign/encr/de sequencer Exp.Mod. 1,959,458 7,838 cr 512 520 Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 521 Exp.Mod. 1024 52,184 4791 1024 RSA verify sequencer Exp.Mod. 2048 187,471 1334 2048 RSA verify sequencer Exp.Mod. 4096 698,057 2,792 4096 SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 522: Modinv Performance
Point addition 43,266 Point doubling 46,246 Point addition 56,403 Point doubling 58,229 Point addition 68,969 Point doubling 70,169 Point addition 84,140 522 Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 523: Ecc-Mul Performance
Sequencer controlled complex operations, this register may not be written and its value is undefined at conclusion of the operation. The driver software can not rely on the written value to remain intact. SWRU319B – April 2012 – Revised April 2013 Security Core Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 524: Pka_Aptr
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CPTR Security Core SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 525: Pka_Alength
These are the Add, Subtract, AddSub, Multiply, Divide, Modulo, Lshift, Rshift, Copy and Compare operations selected directly with bits in the PKA_FUNCTION register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 526: Pka_Blength
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 527: Pka_Msw
These are the Add, Subtract, AddSub, Multiply, Divide, Modulo, Lshift, Rshift, Copy and Compare operations selected directly with bits in the PKA_FUNCTION register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 528: Pka_Ram
– note that the result is only meaningful if no errors were detected and that for ECC operations, the PKA_DIVMSW register will provide information for the x- coordinate of the result point only. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 529: Pka_Seq_Ctrl
The function (and reset state) of bit [31] depends upon the Sequencer program storage option chosen. When using a Sequencer program ROM, the following applies: SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 530: Pka_Options
The hardware reset value is zero, indicating that the information has not been written yet. Table 22-40. PKA_SW_REV PKA_SW_REV, (Read only), 6-bit word offset in control register space: 0x3E SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 531: Pka_Revision
Patches are used to remove bugs without changing the functionality or interface of a module – see the release notes delivered with the package. Bits [23:20], Minor HW revision: 4 bits binary encoding of the minor hardware revision number. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 532: Pka Vector Ram (Pka_Ram)
Interface bus transactions are described in a stylized way, as is the behavior of the main interrupt output (bit [1] of the ‘interrupts’ output bus). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 533: Operation Sequences And Main Interrupt
The bottom sequence (3) shows a highly optimized basic PKCP operations sequence: SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 534: Appendix A: Rsa, Elgamal, Dh, And Dsa Use Cases
M, which must be < n • Compute signature s = M d mod n SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 535: A2: Diffie-Hellman Use Cases
‘A’ calculates (αb mod p)x mod p ≡ αbx mod p • ‘B’ receives αx mod p from ‘A’ and calculates (αx mod p)b mod p ≡ αxb mod p SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 536: A4: Dsa Use Cases
160 bits value (with a modulus of also 160 bits) in the second bullet – the PKA can perform the necessary computations under control of the host SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 537: Aes And Sha Cryptoprocessor
DMA-ed via the DMAC modules. The hash result can either be DMA- ed out or read via the slave interface. To allow keyed hash operations like HMAC, there is an SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 538: Master Control And Interrupts
This results in the following timing: • Write transfers take 2 clock cycles • Read transfers take 3 clock cycles SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 539: Master Bus
0x020DMAC_CH1_CTRLR/W0x00000000Channel 1 control register 0x024DMAC_CH1_EXTADDRR/W0x00000000Channel 1 external address 0x02CDMAC_CH1_DMALENGTHR/W0x00000000Channel 1 DMA length 0x078DMAC_MST_RUNPARAMSR/W0x00006000Master run-time parameters 0x07CDMAC_PERSRR0x00000000Port error raw status register 0x0F8DMAC_OPTIONSR0x00000202DMAC options register SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 540: Register Names And Detail
0x00000000 [95:64] Data Input bits 0x60C HASH_DATA_IN_3 0x00000000 [127:96] Data Input bits 0x610 HASH_DATA_IN_4 0x00000000 [159:128] Data Input bits 0x614 HASH_DATA_IN_5 0x00000000 [191:160] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 541 0x00000000 access on master Master control 0x740 CTRL_SW_RESET 0x00000000 software reset Interrupt 0x780 CTRL_INT_CFG 0x00000000 configuration register Interrupt enabling 0x784 CTRL_INT_EN 0x00000000 register SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 542: Dma Controller And Its Integration
(Outbound) params DMA Controller Crypto engines module Master control Crypto engine Hash engine Key store Figure 22-2. DMA Controller and Its Integration SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 543 The transfer size is at most the block size of the corresponding algorithm. This block size depends on the selected algorithm in the master control module. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 544: Supported Dmac Operations
DMA operation. The ongoing block transfer will be completed, but no new transfers will be requested. PRIO Channel priority: 0 – Low SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 545: Dmac Channel External Address
Therefore, this register must be written last when setting up a DMA channel! Should be written with zeroes and ignored on [31:16] Reserved read SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 546: Dmac Status
1 = enabled (self-cleared to zero). Completion of the software reset must be checked via the DMAC_STATUS register. [31:1] Reserved Bits should be written with a 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 547: Dmac Master Run-Time Parameters
0101b = 32 bytes 0110b = 64 bytes Others = reserved Bits should be written with zeroes and [31:16] Reserved ignored on read SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 548: Dmac Port Error Raw Status
These registers contain information regarding the different options configured in this DMAC. Table 22-53. DMAC Options Register DMAC_OPTIONS, (Read Only), 16 bit Byte address: 0x0F8 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 549: Dmac Version Register
Bits should be ignored on a read. 22.2.3.4 Master Control and Select 22.2.3.4.1 Algorithm Select This algorithm selection register configures the internal destination of the DMA controller. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 550: Master Control Algorithm Select (Ctrl_Alg_Sel)
Hash data is loaded via the DMA, result digest is read via the DMA interface Key store is loaded via the DMA SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 551: Valid Combinations For Ctrl_Alg_Sel Flags
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 552: Interrupt Configuration
Bits should be written with zeroes and [31:1] Reserved ignored on read 22.2.3.4.4.2 Interrupt Enable Table 22-60. Interrupt Enable CTRL_INT_EN, (Read/Write), 32-bit Address Offset: 0x784 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 553: Interrupt Clear
Note that clearing an interrupt only makes sense if the interrupt output is programmed as level (refer to CTRL_INT_CFG) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 554: Interrupt Set
(CTRL_INT_CLR) Bits should be written with zeroes and [31:1] Reserved ignored on read 22.2.3.4.4.5 Interrupt Status SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 555: Interrupt Status
KEY_ST_RD_ERR bit is valid after triggering the key store module to read a key from the memory and providing it to the AES core. 22.2.3.4.5 Version and Configuration Registers 22.2.3.4.5.1 Type and Options Register SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 556: Options Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Patch level EIP-number SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 557: Aes Engine
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_KEY3[31:0] / AES_KEY2[159:128] AES_KEY3[63:32] / AES_KEY2[191:160] AES_KEY3[95:64] / AES_KEY2[223:192] AES_KEY3[127:96] / AES_KEY2[255:224] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 558: Aes_Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_KEY1[31:0] AES_KEY1[63:32] AES_KEY1[95:64] AES_KEY1[127:96] AES_KEY1[159:128] AES_KEY1[191:160] AES_KEY1[223:192] AES_KEY1[255:224] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 559: Key Registers Used Per Key Size
„L‟ must be a copy from the „L‟ value of the AES_CTRL register. This „L‟ indicates the width of the Nonce and counter. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 560: Aes Input/Output Control And Mode Register
If set to „0‟ a decrypt operation is performed. This bit must be written with a „1‟ when CBC-MAC is selected. [4:3] key_size This read-only field specifies the key size. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 561 CCM operations; the length [21:19] CCM-L field in bytes equals the value of CMM-L plus one. All values are supported. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 562 NOTE: Note: Internal operation of the AES module can be interrupted by writing all mode bits to zero and writing zeroes to the length registers (AES_C_LENGTH_0, AES_C_LENGTH_1 and AES_AUTH_LENGTH) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 563: Crypto Data Length Register (Lsw)
Note: For the combined modes (GCM and CCM), this length does not include the authentication only data; the authentication length is specified in the AES_AUTH_LENGTH register below. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 564: Authentication Length Register
Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other Host transfers over the external interface. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 565: Data Input/Output Register
AES_CTRL register must be written. For the modes with authentication (CBC-MAC, GCM and CCM), the invalid (message) bytes/words can be written with any data. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 566: Input/Output Block Format Per Operating Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_TAG[31:0] AES_TAG[63:32] AES_TAG[95:64] AES_TAG[127:96] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 567: Hash Data Input Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 hash_data_in[31:0] … hash_data_in[511:480] SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 568: Hash I/O Buffer Control
In this case, the registers should not be read by the Host. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 569 When „0‟, the hash engine‟s input buffer is processing the data that is currently in HASH_DATA_IN; it is not allowed write new data to these registers. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 570 The Host must write a '1' to this bit to make the intermediate hash digest available. Writing a '0' to this bit has no effect. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 571: Hash Mode Register
When this bit is „0‟ while the hash processing is started, the initial hash algorithm constants are not loaded in the HASH_DIGEST_n registers. The hash engine will SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 572: Hash Length Register
HASH_IO_BUF_CTRL is high. The length register must be written before the last data of the active hash session is written into the hash engine. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 573: Hash Digest Registers
This error is also asserted when the DMA operation writes to ram areas that are not selected. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 574: Key Store Write Area Register
Attempting to write to a key area that already contains a valid key is not allowed and will result in an error. Table 22-85. Key Store Written Area (Status) Register KEY_STORE_WRITTEN_AREA, (Read/Write), 32-bit Address Offset: 0x404 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 575: Key Store Size Register
Section 22.2.3.4.4.5, Interrupt Status. Key store read error will be asserted when a ram area is selected which doesn‟t contain valid written key SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 576: Performance
(„data processing‟) and is fully handled by the hardware. This part is not dependent on the performance of the Host CPU. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 577: Symmetric Crypto Processing Steps
(mode and or keys) the performance is increased. The maximum number of cycles overhead per packet is between 100 and 150 for the various modes and algorithms. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 578: Programming Guidelines
– CTRL_ALG_SEL • Channel control registers with channel bits enabled – DMAC_CH0_CTRL_ADDR – DMAC_CH1_CTRL_ADDR • Channel external address registers – DMAC_CH0_EXTADDR_ADDR – DMAC_CH1_EXTADDR_ADDR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 579: Interrupting Dma Transfers
22.2.5.3 Hashing The hash engine has the following interfaces: SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 580: Data Format And Byte Order
• The interrupt status is observed to check when the engine has completed the operation. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 581 DMAC_CH0_DMALENGTH <length> // input data length in bytes, equal to the message // length write DMAC_CH1_CTRL 0x0000_00001 // enable DMA channel 1 for result digest SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 582: Hmac
K be a secret key padded to the right with extra zeros to the block size of the hash function • m be the message to be authenticated ∥ denote concatenation • • ⊕ denote exclusive or (XOR) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 583: Implementation Of Secure Hmac Operation
The inner digest can be stored back to a pre-allocated area in the external memory such that it can be SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 584: Alternative Basic Hash Where Data Originates From The Slave Interface
HASH_IO_BUF_CTRL[6:0]= 0x42 // indicate that data is available and get the // intermediate digest (no internal padding) // else if final digest is required (input data padded by hash engine) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 585 // digest of the padded data // wait until output data ready wait HASH_IO_BUF_STAT[0] == ’1’ // read digest read HASH_DIGEST_A read HASH_DIGEST_H SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 586: Aes_Key
Keys can only be loaded from external memory using a DMA operation. DMAC channel 0 (inbound) is used for this purpose. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 587: Basic Aes Modes
If the result IV must be read by the Host, the save_context bit must be set to „1‟, after processing the programmed number of bytes. 22.2.5.4.3.3 AES-CTR For AES-CTR operations, the following configuration parameters are required: • Key from the key store module SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 588 AES_CTRL[30]==’1’ // wait for context ready bit [30] read AES_IV_0 read AES_IV_3 // this read clears the ‘saved_context_ready’ flag endif // end of algorithm SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 589: Aes-Gcm
DMAC_CH0_EXTADDR <address> // base address of the AAD data in ext. memory write DMAC_CH0_DMALENGTH <length> // AAD data length in bytes, equal to the aad SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 590: Cbc-Mac
KEY_STORE_READ_AREA[31]==’0’ // wait until the key is loaded to the AES module check CTRL_INT_STAT[29] = ‘0’// check that the key is loaded without errors SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 591: Aes-Ccm
AES-CCM mode. The encrypted result is placed into a pre-allocated area in external memory. The result TAG is read via the slave interface. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 592 AES_CTRL[30]==’1‘ // wait for the context ready bit [30] read AES_TAG_OUT_0 read AES_TAG_OUT_3 // this read clears the ‘saved_context_ready’ flag // end of algorithm SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 593: Exceptions Handling
Note: In case of a read error, the key store writes a key with all bytes set to zero to the AES engine. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 594: Conventions And Compliances
Request for Comments Secure Hash Algorithm SPRAM Single Port Random Access Memory SRAM Static Random Access Memory Tightly Coupled Memory (memory interface protocol) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 595: Terminology
[31:0] indicates a size of 32 bits with most significant bit 31 and least significant bit 0. [11:3] indicates a size of 9 bits with most significant bit 11 and least significant bit 3. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 596: Mapping Of Internal Address Bus To The External Address Bus
– – – PKA RAM (Program RAM) – – – – – – – – – – – – – – – – SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 597: Pkp_Revision
These bits encode the major version number [24:27] Major version number for this module [31:28] Reserved These bits should be ignored on a read 22.3.2.2.1.2 PKP_OPTIONS Register SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 598: Advanced Interrupt Controller (Optional)
Two configuration status registers: module version and module options. Figure 22-5 shows the functional logic of one interrupt bit ‘slice’ and the NOR gate that generates the active LOW interrupt output. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 599: Aic: Functional Logic Of One Interrupt Source
Slave error interrupt. This signal is available as separate output sl_err_int line.When HIGH this indicates slave bus error. Refer to the Section 3.1 for exact condition for specific bus type. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 600: Aic_Pol_Ctrl
PKP, the driver must set each interrupt in this register to level or edge as described in the table below. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 601: Aic_Type_Ctrl
These bits should be written with a ‘0’ and [31:6], [4] Reserved ignored on a read. 22.3.3.4.4 AIC Raw Source Status Register (AIC_RAW_STAT) SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 602: Aic_Raw_Stat
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 603: Aic_Enable_Set
1 = Resets the corresponding bit in the AIC_ENABLE_CTRL register to ‘0’, i.e. disables that interrupt. The activated bit of EnableClear will be cleared internally. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 604: Aic_Options
– as this is version 1.1, the value will be 1 here [31:28] Reserved These bits should be ignored on reading. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 605: Aes Register Summary
0x0000 0000 0x50C 0x4008 B50C AES_AES_KEY2_3 0x0000 0000 0x510 0x4008 B510 AES_AES_KEY3_0 0x0000 0000 0x514 0x4008 B514 AES_AES_KEY3_1 0x0000 0000 0x518 0x4008 B518 AES_AES_KEY3_2 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 606 AES_HASH_DATA_ IN_6 0x0000 0000 0x61C 0x4008 B61C AES_HASH_DATA_ IN_7 0x0000 0000 0x620 0x4008 B620 AES_HASH_DATA_ IN_8 0x0000 0000 0x624 0x4008 B624 AES_HASH_DATA_ IN_9 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 607 0x0000 0000 0x780 0x4008 B780 AES_CTRL_INT_C 0x0000 0000 0x784 0x4008 B784 AES_CTRL_INT_E 0x0000 0000 0x788 0x4008 B788 AES_CTRL_INT_C 0x0000 0000 0x78C 0x4008 B78C AES_CTRL_INT_S SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 608: Aes Register Descriptions
Channel external address value 0x0000 0000 When read during operation, it holds the last updated external address after being sent to the master interface. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 609 A value of 1 indicates that channel 1 is active (DMA transfer on- going). CH0_ACT A value of 1 indicates that channel 0 is active (DMA transfer on- going). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 610 0: Disabled 1: Enable Note: Disabling an active channel interrupts the DMA operation. The ongoing block transfer completes, but no new transfers are requested. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 611 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 612 PORT1_CHANNEL Indicates which channel has serviced last (channel 0 or channel 1) by AHB master port. RESERVED This bit field is reserved. 0x000 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 613 Starts at 0 at first delivery of this version 15:8 EIP_NUMBER_COMP Bit-by-bit complement of the EIP_NUMBER field bits. 0x2E EIP_NUMBER Binary encoding of the EIP-number of this DMA controller (209) 0xD1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 614 Keys that require more than one RAM locations (key size is 192 or 256 bits), must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, or RAM_AREA6. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 615 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 616 Note: This register is reset on a soft reset from the master control module. After a soft reset, all keys must be rewritten to the key store memory. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 617 RAM_AREA6 are the only valid read areas for 192 and 256 bits key sizes. Only RAM areas that contain valid written keys can be selected. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 618 For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 619 For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 620 For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 621 For CCM: -[255:0] - This register is used to store intermediate values. For CBC-MAC: -[255:0] - ZEROES - This register must remain 0. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 622 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_IV SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 623 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_IV SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 624 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 AES_IV SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 625 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CCM_M CCM_L RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 626 Specifies the counter width for AES-CTR mode 00 = 32-bit counter 01 = 64-bit counter 10 = 96-bit counter 11 = 128-bit counter SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 627 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C_LENGTH SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 628 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 C_LENGTH SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 629 A write to this register triggers the engine to start using this context for GCM and CCM. For a host read operation, these registers return all-0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 630 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 631 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 632 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 633 Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 634 AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 635 AES_CTRL register is set. During processing or for operations/modes that do not return a TAG, reads from this register return data from the IV register. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 636 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 637 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 638 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 639 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 640 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 641 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 642 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 643 0s to the next 32-bit boundary. Host read operations from these register addresses return 0s. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 644 HASH_DATA_IN register. In the period between this bit is set by the host and the actual HASH_DATA_IN processing, this bit reads 1. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 645 Note: If this bit is asserted (1) no new operation should be started before the digest is retrieved from the hash engine and this bit is cleared (0). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 646 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LENGTH_IN SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 647 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LENGTH_IN SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 648: Hash Digest Registers
Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 649 Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 650 Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 651 Reading from these registers provides the intermediate hash result (non-final hash operation) or the final hash result (final hash operation) after data processing. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 652 If set to one, selects the AES engine as source/destination for the The read and write maximum transfer size to the DMA engine is set to 16 bytes. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 653 Writing 0 has no effect. The bit is self cleared after executing the reset. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 654 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 655 (irq_result_av) interrupt is not needed. If it is programmed to level, clearing the interrupt output should be done by writing the interrupt clear register (CTRL_INT_CLR). SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 656 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TYPE RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 657: Pka Registers
This section provides information on the PKA module instance within this product. Each of the registers within the module instance is described separately below. Register fields should be considered static unless otherwise noted as dynamic. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 658: Pka Register Summary
Vectors are identified through the location of their least-significant 32-bit word. Note that bit [0] must be zero to ensure that the vector starts at an 8-byte boundary. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 659 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED DPTR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 660 Reset 31:9 RESERVED This bit field is reserved. 0x00 0000 BLENGTH This register specifies the length (in 32-bit words) of Vector B. 0x000 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 661 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 662 PKA_DIVMSW register - can only be used with basic PKCP operations, except for Divide, Modulo and Compare. RESERVED This bit field is reserved. ADDSUB Perform combined add/subtract operation MULTIPLY Perform multiply operation SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 663 RESERVED This bit field is reserved. 10:0 MSW_ADDRESS Address of the most-significant nonzero 32-bit word of the result 0x000 vector in PKA RAM SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 664 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SEQUENCER_STATUS SW_CONTROL_STATUS SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 665: Pka_Program
LNME FIFO RAM size strap input, fifo_size_sel. Note: Reset value is undefined 23:22 RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 666 Values 3-15 are reserved. 27:24 MAJOR_FW_REVISIO 4-bit binary encoding of the major firmware revision number 23:20 MINOR_FW_REVISIO 4-bit binary encoding of the minor firmware revision number SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 667 COMPLEMENT_OF_B Bit-by-bit logic complement of bits [7:0], PKA gives 0xE3 0xE3 ASIC_EIP_NUMBER BASIC_EIP_NUMBER 8-bit binary encoding of the EIP number, PKA gives 0x1C 0x1C SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 668: Radio
23.13 Packet Sniffing and Radio Test Output Signals ............. 23.14 Command Strobe/CSMA-CA Processor ................. 23.15 Register Settings Update ....................23.16 Radio Registers Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 669: Rf Core
NVIC. If a flag is cleared in the RF Core and other unmasked flags are standing, another interrupt is generated. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 670: Interrupt Registers Register Map
Normally, the contents of the TX FIFO are manipulated only by the designated instructions. The TX FIFO can only contain one frame at a time. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 671: Frame Filtering And Source Matching Memory Map
PENDING_OR register bit and the SACK/SACKPEND/SNACK strobes. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 672: Frequency And Channel Programming
= 2405 + 5(k –11) [MHz] k [11, 26] For operation in channel k, the FREQCTRL.FREQ register should therefore be set to FREQCTRL.FREQ = 11 + 5 (k – 11). Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 673: Ieee 802.15.4-2006 Symbol-To-Chip Mapping
1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 674: I And Q Phases When Transmitting A Zero-Symbol Chip Sequence, T
The frame-length field is 7 bits long and has a maximum value of 127. The most-significant bit (MSB) in the frame-length field is reserved, and should always be set to 0 Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 675: Format Of The Frame Control Field (Fcf)
STXONCCA, the receiver is on before the transmission and is turned back on afterward (unless the RXENABLE registers are cleared in the meantime). SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 676: Frame Data Written To The Tx Fifo
TX overflow is indicated when the TX_OVERFLOW interrupt flag is set. When this error occurs, the writing is aborted, (that is, the data byte that caused the overflow is lost). The SFLUSHTX strobe clears the error condition. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 677: Tx Flow Diagram
(that is, the length byte) are transmitted. 23.8.6 TX Flow Diagram Figure 23-6 summarizes the transmitter flow in a flow diagram: SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 678: Tx Flow
TX strobe) TX strobe) TX strobe) Figure 23-6. TX Flow Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 679: Transmitted Synchronization Header
FCS and write it to the TX FIFO with the rest of the MPDU. Figure 23-8 shows the hardware implementation of the FCS calculator. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 680: Fcs Hardware Implementation
The RF output power is controlled by the 8-bit value in the TXPOWER register. The data sheet for the CC2538 device shows typical output power and current consumption for recommended settings when the center frequency is set to 2.440 GHz. The recommended settings are only a small subset of all the possible register settings.
Page 681: Rx State Timing
The SFD signal, which can be output on GPIO, can be used to capture the start of received frames (see Figure 23-9): SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 682: Sfd Signal Timing
PAN identifier (0xFFFF). – If a short destination address is included in the frame, it must match either SHORT_ADDR or the broadcast address (0xFFFF). Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 683: Interrupts
RX_OVERFLOW or RX_FRM_ABORTED is generated before the filtering result is known. Figure 23-10 shows the three different scenarios (not including the overflow and abort-error conditions). SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 684: Filtering Scenarios (Exceptions Generated During Reception)
FRMFILT1 register to control the expected receipt of acknowledgment frames: • Set the ACCEPT_FT2_ACK bit of the FRMFILT1 register after successfully starting a transmission Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 685: Source Address Matching
A short address entry starts with the 16-bit PAN_ID followed by the 16-bit short address. These entries are stored at address 0x4008 8400 + (16 × n), where n is a number from 0 to 23. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 686: Matching Algorithm For Short And Extended Addresses
Figure 23-11. Matching Algorithm for Short and Extended Addresses SRCRESMASK and SRCRESINDEX are written to RF Core memory as soon as the result is available. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 687: Interrupts Generated By Source Address Matching
Read the results from RAM before RX_FRM_ACCEPTED occurs in the next received frame. For the shortest frame type, this occurs after the sequence number, so the total available time (absolute worst- SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 688: Data In Rx Fifo For Different Settings
The generated acknowledgment frame contains three variable fields: • The pending bit, which may be controlled with command strobes and the AUTOPEND feature (in the Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 689: Acknowledgement Timing
The acknowledgment request bit must be set in the RX frame. • The RX frame must not be a beacon or an acknowledgment frame. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 690: Automatic Setting Of The Frame Pending Field (Autopend)
– The number of bytes in RX FIFO is greater than FIFOPCTRL.FIFOP_THR after frame filtering. – There is atleast one complete frame in the RX FIFO. – RX FIFO overflows. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 691: Behavior Of Fifo And Fifop Signals
(128 μs) as specified by the IEEE 802.15.4 standard. The RSSI value is a 2s-complement signed number on a logarithmic scale with 1-dB steps. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 692: Link Quality Indication
Controls the data flow within the RF Core • Generates automatic acknowledgement frames • Controls all analog RF calibration Figure 23-18 shows the main FSM. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 693: Main Fsm
RX or RX wait 0x0E RX FIFO reset 0x10 RX overflow 0x11 TX calibration 0x20 34–38 0x22–0x26 TX final 0x27 TX or RX transit 0x28 SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 694: Fft Of The Random Bytes
–10 –20 –30 –40 –50 –60 –70 –80 –3 –2 –1 f – frequency (radians) Figure 23-19. FFT of the Random Bytes Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 695: Histogram Of 20 Million Bytes Generated With The Random Instruction
(rfc_obs_sig); for example, for packet sniffing, one needs the rfc_sniff_data for the packet sniffer data signal and rfc_sniff_clk for the corresponding clock signal. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 696: Command Strobe/Csma-Ca Processor
CPU. These registers are read or modified by some instructions, thus letting the CPU set parameters for a CSP program, or letting the CPU read the status of a CSP program. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 697: Program Execution
ISSTART command. To clear the program contents, use the ISCLEAR instruction. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 698: Running A Csp Program
CSP X register G_CSPX RFCORE_XRE 0x18C CSPY 0x0000 0000 CSP Y register G_CSPY RFCORE_XRE 0x190 CSPZ 0x0000 0000 CSP Z register G_CSPY 698 Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 699: Instruction Set Summary
Execution continues as soon as X = 0. (If X = 0 when WAITX instruction is run, no wait is performed and execution continues directly.) An IRQ_CSP_WAIT interrupt request is generated when execution continues. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 700: Instruction Set Definition
Description: The Z register is decremented by 1. An original value of 0x00 underflows to 0xFF. Operation: Z = Z – 1 Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 701: Decy
The Y register is incremented by 1. An original value of 0xFF overflows to 0x00. Operation: Y = Y + 1 Opcode: 0xC1 23.14.9.6 INCX SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 702: Incmaxy
23.14.9.9 INT Function: Interrupt Description: The interrupt IRQ_CSP_INT is asserted when this instruction executes. Operation: IRQ_CSP_INT = 1 Opcode: 0xBA 23.14.9.10 WAITX Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 703: Setcmp1
Operation: PC = PC while MAC timer compare = false PC = PC + 1 when MAC timer compare = true SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 704: Wevent2
Reserved Register X = 0 X = 0 Register Y = 0 Y = 0 Register Z = 0 Z = 0 Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 705: Skip S, C
Opcode: 0x00 | S | N | C 23.14.9.18 STOP Function: Stop program execution Description: The SSTOP instruction stops the CSP program execution. Operation: Stop execution SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 706: Snop
Enable calibration and TX if CCA indicates a clear channel Description: The STXONCCA instruction enables TX after calibration if CCA indicates a clear channel. Operation: STXONCCA Opcode: 0xDA Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 707: Ssamplecca
The SFLUSHTX instruction flushes the TX FIFO buffer. The instruction waits for the radio to acknowledge the command before executing the next instruction. Operation: SFLUSHTX Opcode: 0xDE 23.14.9.27 SACK SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 708: Sackpend
Set bit in RXENABLE register Description: The SRXMASKBITSET instruction sets bit [5] in the RXENABLE register. Operation: SRXMASKBITSET Opcode: 0xD4 23.14.9.31 SRXMASKBITCLR Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 709: Isstop
Opcode: 0xE3 23.14.9.35 ISRXMASKBITSET Function: Set bit in RXENABLE Description: The ISRXMASKBITSET instruction immediately sets bit [5] in the RXENABLE register. Operation: SRXMASKBITSET SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 710: Isrxmaskbitclr
Sample the current CCA value to SAMPLED_CCA Description: The current CCA value is immediately written to SAMPLED_CCA in XREG. Operation: SSAMPLECCA Opcode: 0xEB Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 711: Isrfoff
The ISACKPEND instruction immediately sends an acknowledge frame with the pending field set. The instruction waits for the radio to receive and interpret the command before executing the next instruction. SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 712: Registers That Require Update From Their Default Value
Adjusts AGC target value. TXFILTCFG 0x09 Sets TX anti-aliasing filter to appropriate bandwidth. IVCTRL 0x0B Controls bias currents. FSCAL1 0x01 Tune frequency calibration Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 713: Rfcore_Ffsm Register Summary
XT_ADDR5 0x0000 0000 0xC0 0x4008 85C0 RFCORE_FFSM_E XT_ADDR6 0x0000 0000 0xC4 0x4008 85C4 RFCORE_FFSM_E XT_ADDR7 0x0000 0000 0xC8 0x4008 85C8 RFCORE_FFSM_P AN_ID0 SWRU319B – April 2012 – Revised April 2013 Radio Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 714: Rfcore_Ffsm Register Descriptions
0x00 0000 SRCRESMASK1 Short address matching 0x00 When there is a match on entry panid_n + short_n, bit n is set in SRCRESMASK. Radio SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 715 0x00 pending for each of the 12 extended addresses. Entry n is mapped to SRCEXTPENDEN[2n]. All SRCEXTPENDEN[2n + 1] bits are don't care. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 716 0x00 0000 SRCSHORTPENDEN0 8 LSBs of the 24-bit mask that enables or disables automatic 0x00 pending for each of the 24 short addresses SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 717 Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 EXT_ADDR0 EXT_ADDR[7:0] 0x00 The IEEE extended address used during destination address filtering SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 718 Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 EXT_ADDR3 EXT_ADDR[31:24] 0x00 The IEEE extended address used during destination address filtering SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 719 Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 EXT_ADDR6 EXT_ADDR[55:48] 0x00 The IEEE extended address used during destination address filtering SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 720 Description Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 PAN_ID1 PAN_ID[15:8] 0x00 The PAN ID used during destination address filtering SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 721: Rfcore_Xreg Register Summary
RFCORE_XREG_F RMFILT1 0x0000 0007 0x008 0x4008 8608 RFCORE_XREG_S RCMATCH 0x0000 0000 0x00C 0x4008 860C RFCORE_XREG_S RCSHORTEN0 0x0000 0000 0x010 0x4008 8610 RFCORE_XREG_S RCSHORTEN1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 722 RFCORE_XREG_R XFIRST 0x0000 0000 0x06C 0x4008 866C RFCORE_XREG_R XFIFOCNT 0x0000 0000 0x070 0x4008 8670 RFCORE_XREG_T XFIFOCNT 0x0000 0000 0x074 0x4008 8674 RFCORE_XREG_R XFIRST_PTR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 723 RFCORE_XREG_A GCCTRL2 0x0000 002E 0x0D0 0x4008 86D0 RFCORE_XREG_A GCCTRL3 0x0000 0010 0x0D4 0x4008 86D4 RFCORE_XREG_A DCTEST0 0x0000 000E 0x0D8 0x4008 86D8 RFCORE_XREG_A DCTEST1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 724: Rfcore_Xreg Register Descriptions
0x1B0 0x4008 87B0 RFCORE_XREG_R FC_OBS_CTRL1 0x0000 0000 0x1B4 0x4008 87B4 RFCORE_XREG_R FC_OBS_CTRL2 0x0000 000F 0x1E8 0x4008 87E8 RFCORE_XREG_T XFILTCFG 23.16.2.2 RFCORE_XREG Register Descriptions SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 725 FRMFILT1[7:1], together with the local address information, define the behavior of the filtering algorithm. 0: Frame filtering off. (FRMFILT0[6:1], FRMFILT1[7:1] and SRCMATCH[2:0] are don't care.) 1: Frame filtering on. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 726 10: Set MSB of the frame type to 0. 11: Set MSB of the frame type to 1. RESERVED This bit field is reserved. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 727 Optional safety feature: To ensure that an entry in the source matching table is not used while it is being updated, set the corresponding SHORT_ADDR_EN bit to 0 while updating. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 728 Optional safety feature: To ensure that an entry in the source matching table is not used while it is being updated, set the corresponding EXT_ADDR_EN bit to 0 while updating. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 729 1: RSSI + The CRC_OK bit and the 7-bit SRCRESINDEX are appended at the end of each received frame. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 730 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED Reserved SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 731 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RXENMASKSET SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 732 (1111) switches in extra capacitance to the oscillator, effectively lowering the XOSC frequency. Hence, a higher setting gives a higher frequency. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 733 Bits Field Name Description Type Reset 31:8 RESERVED This bit field is reserved. 0x00 0000 PA_POWER PA power control PA_BIAS PA bias control SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 734 0: Calibration is complete or not started. 1: Calibration is in progress. FSM_FFCTRL_STATE Gives the current state of the FIFO and frame control (FFCTRL) 0x00 finite state-machine. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 735 31:8 RESERVED This bit field is reserved. 0x00 0000 RESERVED This bit field is reserved. FIFOP_THR Threshold used when generating FIFOP signal 0x40 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 736 CCA signal never indicates a clear channel. This register should be updated to 0xF8, which translates to an input level of about -8 - 73 = -81 dBm. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 737 The reset value of -128 also indicates that the RSSI value is invalid. RFCORE_XREG_RSSISTAT Address offset 0x064 Physical Address 0x4008 8664 Instance RFCORE_XREG Description RSSI valid status register Type SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 738 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED TXFIFOCNT SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 739 This bit field is reserved. 0x00 0000 RXP1_PTR RAM address offset of the first byte of the first frame in the RX FIFO 0x00 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 740 Bit mask is masking out interrupt sources. 0x00 Bit position: 7: RXMASKZERO 6: RXPKTDONE 5: FRAME_ACCEPTED 4: SRC_MATCH_FOUND 3: SRC_MATCH_DONE 2: FIFOP 1: SFD 0: ACT_UNUSED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 741 Bit mask is masking out interrupt sources. 0x00 Bit position: 6: STROBE_ERR 5: TXUNDERF 4: TXOVERF 3: RXUNDERF 2: RXOVERF 1: RXABO 0: NLOCK SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 742 Random bit from the I channel of the receiver RFCORE_XREG_MDMCTRL0 Address offset 0x0A0 Physical Address 0x4008 86A0 Instance RFCORE_XREG Description Controls modem Type SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 743 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CORR_THR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 744 Adjusts front-end LNA PTAT current output (from M = 3 to M = 6), default: M = 5 MIX_CURRENT Control of the output current from the receiver mixers The current increases with increasing setting set. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 745 CHP_DISABLE Set this bit to manually disable charge pump by masking the up and down pulses from the phase detector. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 746 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED VCO_CAPARR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 747 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED AGC_DR_XTND_THR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 748 When read, this register returns the current applied gain setting. 00: 0-dB gain (reference level) 01: 3-dB gain 10: Reserved 11: 6-dB gain SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 749 10: 3-dB attenuation in AAF 11: 0-dB attenuation in AAF (reference level) AAF_RP_OE Override the AAF control signals of the AGC with the values stored in AAF_RP. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 750 0x00 0000 ADC_TEST_CTRL ADC test mode selector ADC_C2_ADJ Used to adjust capacitor values in ADC ADC_C3_ADJ Used to adjust capacitor values in ADC SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 751 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED TX_TONE SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 752 0: Use the normal IF frequency (MDMTEST0.TX_TONE) for automatic IF compensation of channel frequency on TX. 1: Use mirror IF frequency for automatic compensation of channel frequency on TX. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 753 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED DAC_I_O SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 754 101: RSSI I output on the I DAC 111: Reserved RFCORE_XREG_ATEST Address offset 0x0F4 Physical Address 0x4008 86F4 Instance RFCORE_XREG Description Analog test control Type SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 755 11: PD When PD_OVERRIDE = 1 TXMIX_PD Transmit mixer power-down signal When PD_OVERRIDE = 1 AAF_PD Antialiasing filter power-down signal When PD_OVERRIDE = 1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 756 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 757 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED CSPY SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 758 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RFC_OBS_MUX0 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 759 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED RFC_OBS_MUX1 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 760: Rfcore_Sfr Registers
This section provides information on the RFCORE_SFR module instance within this product. Each register within the module instance is described separately below. Register fields should be considered static unless otherwise noted as dynamic. SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 761: Rfcore_Sfr Register Summary
Triggered if trying to disable the radio when it is already disabled, or when trying to do a SACK, SACKPEND, or SNACK command when not in active RX. 0: No interrupt pending 1: Interrupt pending SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 762 A complete frame has been transmitted. 0: No interrupt pending 1: Interrupt pending TXACKDONE An acknowledgement frame has been completely transmitted. 0: No interrupt pending 1: Interrupt pending SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 763 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED INSTR SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 764: Cctest Register Summary
This bit field is reserved. 0x0000 0000 I/O strength control bit Common to all digital output pads Should be set when unregulated voltage is below approximately 2.6 SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 765 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 766 Note: If enabled, this overwrites the standard GPIO behavior of PC4. n - obs_sigs[n] output on output 4: 0x00 0: rfc_obs_sig0 1: rfc_obs_sig1 2: rfc_obs_sig2 Others: Reserved SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 767 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 768: Ana_Regs Registers
This bit must be 1 as well as the stand-by control from the USB controller, before the mode of the PHY is stand-by. 23.16.5 ANA_REGS Registers SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 769: Ana_Regs Register Summary
Controls bias current to PA 00: IREF bias 01: IREF and IVREF bias (CC2530 mode) 10: PTAT bias 11: Increased PTAT slope bias SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 770: Voltage Regulator
The digital voltage regulator is used to power the digital core. The output of this regulator is available on the DCOUPL pin and requires capacitive decoupling to function properly (for example, see the reference design of the CC2538 device). The voltage regulator is disabled in power modes PM2 and PM3. When the voltage regulator is disabled, most of the register and RAM contents are retained while the unregulated 2- to 3.6-V power supply is...
Page 771 Appendix A SWRU319B – April 2012 – Revised April 2013 Available Software This chapter presents the various available software solutions relevant to the CC2538 SoC. They are all available free of charge on the TI Web site at www.ti.com/lprf when used with TI LPRF devices.
Page 772: A.1 Smartrf™ Studio Software For Evaluation (Www.ti.com/Smartrfstudio)
SmartRF Studio software runs on Microsoft™ Windows™ XP (32 bit), Windows Vista (32 & 64 bit) and Windows 7 (32 & 64 bit). SmartRF Studio can be downloaded from the Texas Instruments Web page: www.ti.com/smartrfstudio.
Page 773 • Wireless sensor networks • Alarm and security • Asset tracking • Applications that require interoperability For more information, visit the Texas Instruments Z-Stack™ software page: www.ti.com/z-stack. SWRU319B – April 2012 – Revised April 2013 Available Software Submit Documentation Feedback...
Page 774 Effective number of bits ETSI European Telecommunications Standards Institute Error vector magnitude Federal Communications Commission Frame control field Frame check sequence 774 Abbreviations SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 775 O-QPSK Offset – quadrature phase-shift keying Power amplifier Program counter Printed circuit board Packet error rate PHY header Physical layer Phase-locked loop SWRU319B – April 2012 – Revised April 2013 Abbreviations Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 776 Test reset Transistor-transistor logic Transmit UART Universal asynchronous receiver/transmitter USART Universal synchronous/asynchronous receiver/transmitter Voltage-controlled oscillator Variable-gain amplifier Watchdog timer XOSC Crystal oscillator Abbreviations SWRU319B – April 2012 – Revised April 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated...
Page 777: Additional Information
RF transceivers, RF transmitters, RF front ends and System-on-Chips as well as various software solutions for the sub-1 and 2.4-GHz frequency bands. In addition, Texas Instruments provides a large selection of support collateral such as development tools, technical documentation, reference designs, application expertise, customer support, third-party and university programs.
Page 778: C.1 Texas Instruments Low-Power Rf Web Site
Texas Instruments Low-Power RF Web Site www.ti.com Texas Instruments Low-Power RF Web Site Texas Instruments’ Low-Power RF Web site has all our latest products, application and design notes, FAQ section, news and events updates, and much more. Just go to www.ti.com/lprf. Low-Power RF Online Community •...
Page 779 Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf 2. CC2538 Data Sheet http://www.ti.com/lit/ds/symlink/cc2538.pdf 3. CC2538 ROM User's Guide 4. CC2538 Driver Library User's Guide 5. Universal Serial Bus Specification Rev. 2.0 SWRU319B – April 2012 – Revised April 2013 References Submit Documentation Feedback Copyright ©...
Page 780: E.1 Revision History – External
SWRU319 April 2012 SWRU319A November 2012 SWRU319B April 2013 CC2538 User's Guide, (SWRU319) - initial release. CC2538 User's Guide Version A, (SWRU319A): • Most of resolved and closed action items have been updated. CC2538 User's Guide Version B, (SWRU319B): •...
Page 781: Important Notice
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.