Texas Instruments CC2538 Manuals

Manuals and User Guides for Texas Instruments CC2538. We have 3 Texas Instruments CC2538 manuals available for free PDF download: User Manual, Quick Start Manual

Texas Instruments CC2538 User Manual (781 pages)

System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee/ZigBee IP Applications

Brand: Texas Instruments | Category: Switch | Size: 4 MB

Table of Contents

3
- Document Conventions
  26
- Preface
  26
- Architectural Overview
  32
  - Target Applications
    33
  - Overview
    33
- CC2538 Block Diagram
  34
  - Functional Overview
    36
    
    ARM Cortex-M3
    36
    
    Memory Map
    36
    
    Processor Core
    36
    
    System Timer (Systick)
    36
    
    Flash Memory
    37
    
    Mpu
    37
    
    Nested Vector Interrupt Controller
    37
    
    On-Chip Memory
    37
    
    Sram
    37
    
    System Control Block
    37
    
    AES Engine with 128, 192 256 Bit Key Support
    38
    
    Programmable Timers
    38
    
    Radio
    38
    
    Rom
    38
    
    CCP Pins
    39
    
    Direct Memory Access
    39
    
    MAC Timer
    39
    
    Sleep Timer
    39
    
    Watchdog Timer
    39
    
    System Control and Clock
    40
    
    Serial Communications Peripherals
    41
    
    Uart
    41
    
    Usb
    41
    
    I 2 C
    42
    
    Analog
    43
    
    Programmable Gpios
    43
    
    Ssi
    43
    
    Adc
    44
    
    Analog Comparator
    44
    
    Cjtag, JTAG and SWO
    44
    
    Packaging and Temperature
    44
    
    Random Number Generator
    44
- The Cortex-M3 Processor
  45
  - The Cortex-M3 Processor Introduction
    46
  - Block Diagram
    46
  - Overview
    47
    
    Integrated Configurable Debug
    47
    
    System-Level Interface
    47
- CPU Block Diagram
  47
- Interrupts
  47
- TPIU Block Diagram
  48
- Summary of Processor Mode, Privilege Level, and Stack Use
  49
- Cortex-M3 Register Set
  50
- Processor Register Map
  50
  - Register Descriptions
    51
- PSR Register Combinations
  56
  - Exceptions and Interrupts
    61
  - Data Types
    61
  - Instruction Set Summary
    61
- Cortex-M3 Instruction Summary
  61
- Cortex™-M3 Peripherals
  65
  - Cortex™-M3 Peripherals Introduction
    66
  - Functional Description
    66
    
    Systick
    66
- Core Peripheral Register Regions
  66
  - Nvic
    67
    
    Hardware and Software Control of Interrupts
    67
    
    Level-Sensitive and Pulse Interrupts
    67
    
    Mpu
    68
    
    Scb
    68
    
    Updating an MPU Region
    69
    
    Updating an MPU Region Using Separate Words
    69
- Memory Attributes Summary
  69
  - Updating an MPU Region Using Multiple-Word Writes
    70
  - Subregions
    70
    
    MPU Access Permission Attributes
    71
- SRD Use Example
  71
- TEX, S, C, and B Bit Field Encoding
  71
  - MPU Configuration for a CC2538 Microcontroller
    72
    
    MPU Mismatch
    72
  - Register Map
    72
- AP Bit Field Encoding
  72
- Cache Policy for Memory Attribute Encoding
  72
- Memory Region Attributes for a CC2538 Microcontroller
  72
- Peripherals Register Map
  73
  - Systick Register Descriptions
    75
  - Bus
    75
- Faults
  75
  - NVIC Register Descriptions
    77
- Interrupt Enable
  78
  - System Control Block (SCB) Register Descriptions
    127
  - MPU Register Descriptions
    144
- Memory Map
  157
  - Memory Model
    158
    
    Memory Regions, Types, and Attributes
    159
    
    Behavior of Memory Accesses
    160
    
    Memory System Ordering of Memory Accesses
    160
    
    Software Ordering of Memory Accesses
    160
- Memory Access Behavior
  160
  - Bit-Banding
    161
- Peripheral Memory Bit-Banding Regions
  162
  - Directly Accessing an Alias Region
    163
  - Directly Accessing a Bit-Band Region
    163
    
    Data Storage
    163
- SRAM Memory Bit-Banding Regions
  162
- Bit-Band Mapping
  163
  - Synchronization Primitives
    164
- Data Storage
  164
- Interrupts
  166
  - Exception Model
    167
    
    Exception States
    167
    
    Exception Types
    167
    
    Interrupts
    169
    
    Exception Handlers
    172
    
    Vector Table
    172
    
    Exception Priorities
    173
- Vector Table
  173
  - Interrupt Priority Grouping
    174
  - Exception Entry and Return
    174
    
    Exception Entry
    174
    
    Exception Return
    175
- Exception Return Behavior
  175
  - Fault Handling
    176
- Exception Stack Frame
  175
- Fault Status and Fault Address Registers
  177
  - Fault Escalation and Hard Faults
    177
  - Lockup
    178
- JTAG Interface
  179
- IEEE 1149.7 Signals
  180
  - Debug Port
    180
- Test/Debug System Top Level Diagram
  180
- IEEE 1149.7 Features Subset
  181
- Data Register Description for 0X0A
  185
  - CM3 Debug Interrupt
    185
    
    System Control
    186
    
    Power Management
    187
- Data Register Description for Instruction 0X0E(Read Only)
  185
- Flow Diagram for Operational Modes
  188
- Power Management Matrix
  188
  - Using Power Management
    188
    
    Sequencing When Using Power Modes
    189
- Simple Flow Diagram for Power Management
  190
  - Time Considerations for Active, Sleep and PM0
    190
    
    Enter Power Mode When Running on 16 Mhz System Clock
    191
- Timing Example for Transition from 32 Mhz to Pm's
  192
- Block Diagram Oscillators and Clocks
  195
  - Mhz RCOSC Calibration
    196
- Clock Gate Matrix
  197
  - Clocks for UART and SSI
    197
  - Reset of Peripherals
    198
- SYS_CTRL Register Summary
  199
  - Emulator in Power Modes
    199
    
    SYS_CTRL Register Descriptions
    201
Internal Memory

217
- Chapter 8
  
  218
  - Flash Memory Organization
    218
  - Flash Write
    218
  - Introduction
    218
  - Example Write Sequence
    219
    
    Writing Multiple Times to a Word
    219
    
    DMA Flash Write
    220
  - Flash Write Using DMA
    221
    
    CPU Flash Write
    221
  - Flash Size Configuration
    222
    
    Flash
    222
    
    Flash DMA Trigger
    222
    
    Flash Lock Bit Page and Customer Configuration Area (CCA)
    222
  - Upper 32 Bytes of Lock Bit Page and CCA Layout
    223
  - Bitfield of the Lock Bit Page
    224
    
    Flash Image Valid Bits in Lock Bit
    224
  - Fields at POR/ Reset
    224
  - Flash Controller Priorities
    225
    
    Flash Mass Erase
    225
  - Layout of Byte 2007
    225
  - Data Register Description for Instruction 0X0E (READ ONLY)
    226
    
    Flash Mass Erase Procedure
    226
    
    ROM Sub System
    227
    
    Sram
    227
  - Icepick TAP State
    226
  - FLASH_CTRL Register Summary
    228
    
    Flash Control Registers
    228
  - General-Purpose Inputs/Outputs
    234
  - Pheripheral Signal Select Values (same for All Ioc_Pxx_Sel Registers)
    235
    
    I/O Control
    235
    
    Gpio
    236
  - Digital I/O Pads (the Diagram Shows One of 32 Possible I/O Pins)
    237
    
    Data Control
    237
  - GPIODATA Read Example
    238
    
    Data Direction Operation
    238
    
    Power-Up Interrupt
    239
  - GPIODATA Write Example
    238
  - PAD Configuration Override Registers
    240
    
    Pad Control
    240
    
    Configuration
    241
  - GPIO Common Registers Mapping Summary
    242
  - GPIO Register Summary
    242
    
    GPIO Instances Register Mapping Summary
    242
  - GPIO Register Summary
    243
  - GPIO Register Summary
    244
    
    GPIO Common Register Descriptions
    245
    
    IOC Registers
    259
  - IOC Register Summary
    260
    
    IOC Register Descriptions
    262
  - Micro Direct Memory Access
    290
    
    Μdma Introduction
    291
  - Μdma Block Diagram
    292
    
    Functional Description
    292
  - Μdma Channel Assignments
    293
    
    Priority
    294
  - Control Structure Memory Map
    295
    
    Single Request
    295
  - Request Type Support
    295
  - Channel Control Structure
    296
    
    Transfer Modes
    296
    
    Basic Mode
    297
  - Example of Ping-Pong Μdma Transaction
    298
    
    Memory Scatter-Gather
    298
  - Memory Scatter-Gather, Setup and Configuration
    300
  - Memory Scatter-Gather, Μdma Copy Sequence
    301
    
    Peripheral Scatter-Gather
    302
  - Peripheral Scatter-Gather, Setup and Configuration
    303
  - Peripheral Scatter-Gather, Μdma Copy Sequence
    304
  - Μdma Read Example: 8-Bit Peripheral
    305
    
    Transfer Size and Increment
    305
  - Μdma Interrupt Assignments
    306
    
    Interrupts and Errors
    306
  - Channel Control Structure Offsets for Channel
    307
  - Channel Control Word Configuration for Memory Transfer Example
    307
    
    Configure the Channel Control Structure
    307
  - Channel Control Structure Offsets for Channel
    308
  - Channel Control Word Configuration for Peripheral Transmit Example
    308
    
    Configuring a Peripheral for Simple Transmit
    308
    
    Start the Transfer
    309
  - Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
    310
    
    Configure the Source and Destination
    310
  - Primary and Alternate Channel Control Structure Offsets for Channel 8
    310
  - UDMA Register Summary
    311
    
    Enable the Μdma Channel
    311
    
    UDMA Register Descriptions
    312
  - General-Purpose Timers
    324
  - GPTM Module Block Diagram
    325
    
    General-Purpose Timers
    325
  - General-Purpose Timer Capabilities
    326
    
    Functional Description
    326
    
    Timer Modes
    327
  - Counter Values When the Timer Is Enabled in Input Edge-Count Mode
    328
  - Counter Values When the Timer Is Enabled in Input Event-Count Mode
    329
  - Input Edge-Count Mode Example, Counting down
    329
  - Input Edge-Time Mode Example
    330
    
    PWM Mode
    330
  - Counter Values When the Timer Is Enabled in PWM Mode
    331
  - Bit PWM Mode Example
    332
    
    Wait-For-Trigger Mode
    333
  - Time-Out Actions for GPTM Modes
    334
    
    Synchronizing GP Timer Blocks
    334
    
    Initialization and Configuration
    335
    
    Input Edge_Timing Mode
    336
  - Timer Daisy-Chain
    334
  - GPTIMER Common Registers Mapping Summary
    337
    
    General-Purpose Timer Registers
    337
  - GPTIMER Register Summary
    338
  - GPTIMER Register Summary
    339
    
    GPTIMER Common Register Descriptions
    341
    
    MAC Timer
    356
    
    Timer Operation
    357
    
    Overflow Count
    358
    
    Event Outputs (DMA Trigger and Radio Events)
    359
    
    Timer Synchronous Start
    360
    
    MAC Timer Registers
    361
    
    RFCORE_SFR Register Descriptions
    362
    
    Sleep Timer
    368
    
    General
    369
  - Sleep Timer Capture
    370
    
    Sleep Timer Registers
    370
  - SMWDTHROSC Register Summary
    371
    
    SMWDTHROSC Register Descriptions
    371
  - Watchdog Timer
    376
  - SMWDTHROSC Register Summary
    377
    
    Watchdog Timer
    377
  - ADC Block Diagram
    380
    
    ADC Introduction
    380
    
    ADC Conversion Sequences
    381
    
    ADC Conversion Results
    382
    
    Analog-To-Digital Converter Registers
    383
    
    Random Number Generator
    387
  - Basic Structure of the RNG
    388
    
    Introduction
    388
    
    Crc16
    389
    
    Analog Comparator
    391
  - Analog Comparator
    392
    
    Introduction
    392
    
    SOC_ADC Register Summary
    393
  - Universal Asynchronous Receivers and Transmitters
    394
    
    Universal Asynchronous Receivers and Transmitters
    395
  - Signals for UART (64LQFP)
    396
    
    Signal Description
    396
  - UART Module Block Diagram
    396
  - UART Character Frame
    397
    
    Functional Description
    397
    
    Data Transmission
    398
  - Flow Control Mode
    399
    
    LIN Support
    399
  - LIN Message
    399
  - LIN Synchronization Field
    400
    
    Bit UART Mode
    400
    
    Interrupts
    401
  - UART Common Registers Mapping Summary
    402
  - UART Register Summary
    403
    
    UART Instances Register Mapping Summary
    403
  - UART Register Summary
    404
    
    UART Common Register Descriptions
    404
    
    Synchronous Serial Interface
    422
  - SSI Module Block Diagram
    423
    
    Block Diagram
    423
  - Synchronous Serial Interface
    423
  - Signals for SSI (64LQFP)
    424
    
    Signal Description
    424
    
    Receive FIFO
    425
  - TI Synchronous Serial Frame Format (Continuous Transfer)
    426
    
    Texas Instruments Synchronous Serial Frame Format
    426
  - TI Synchronous Serial Frame Format (Single Transfer)
    426
  - Freescale SPI Format (Continuous Transfer) with SPO = 0 and SPH
    427
    
    SPO Clock Polarity Bit
    427
  - Freescale SPI Format (Single Transfer) with SPO = 0 and SPH
    427
  - Freescale SPI Frame Format (Single Transfer) with SPO = 1 and SPH
    428
  - Freescale SPI Frame Format with SPO = 0 and SPH
    428
  - Freescale SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH
    429
  - Freescale SPI Frame Format with SPO = 1 and SPH
    429
  - MICROWIRE Frame Format (Single Frame)
    430
  - MICROWIRE Frame Format (Continuous Transfer)
    431
  - MICROWIRE Frame Format, Ssifss Input Setup and Hold Requirements
    431
    
    DMA Operation
    431
  - SSI Common Registers Mapping Summary
    433
  - SSI Register Summary
    433
  - SSI Register Summary
    434
    
    SSI Common Register Descriptions
    434
    
    Inter-Integrated Circuit Interface
    441
    
    Bus Configuration
    442
  - Inter-Integrated Circuit Interface
    442
  - Start and Stop Conditions
    443
  - Complete Data Transfer with a 7-Bit Address
    444
  - Data Validity During Bit Transfer on the I
    444
  - R/S Bit in First Byte
    444
  - Examples of I
    445
  - Master Timer Period Versus Speed Mode
    445
    
    Arbitration
    445
    
    Loopback Operation
    446
  - Master Single TRANSMIT
    447
  - Master Single RECEIVE
    448
  - Master TRANSMIT with Repeated Start Condition
    449
  - Master RECEIVE with Repeated Start Condition
    450
  - Master RECEIVE with Repeated Start after TRANSMIT with Repeated Start Condition
    451
  - Master TRANSMIT with Repeated Start after RECEIVE with Repeated Start Condition
    452
  - Slave Command Sequence
    453
    
    Initialization and Configuration
    453
  - I2CM Register Summary
    454
  - I2CS Register Summary
    459
Usb Controller

464
- Chapter 21
  
  465
  - 48-Mhz USB PLL
    465
  - USB Controller Block Diagram
    465
  - USB Enable
    465
  - USB Introduction
    465
  - USB Interrupt Flags and Associated Interrupt-Enable Mask Registers
    466
    
    USB Interrupts
    466
  - USB Interrupt Service Routine
    467
    
    USB Reset
    467
  - Endpoint 0
    468
    
    Zero Data Requests
    469
    
    Endpoint 0 Interrupts
    470
    
    Read Requests
    470
  - USB Index Register
    468
  - USB Suspend and Resume
    468
  - Endpoint 0 States
    472
  - Endpoint 0 Service Routine
    473
    
    Error Conditions
    474
  - SETUP Phase of Control Transfer
    475
  - SETUP Phase Control Transactions
    476
    
    IN Transactions (TX State)
    476
  - IN Data Phase for Control Transfer
    477
  - IN Phase Control Transactions
    478
  - Control Transactions Following Status Stage (TX Mode)
    479
    
    OUT Transactions (RX State)
    479
  - OUT Data Phase for Control Transfer
    480
  - OUT Phase Control Transactions
    481
  - Control Transactions Following Status Stage (RX Mode)
    482
    
    Endpoints 1-5
    482
  - FIFO Sizes for EP1-EP5
    483
    
    FIFO Management
    483
    
    FIFO Access
    484
  - IN/OUT Fifos
    483
  - Bulk and Interrupt in Transactions
    486
    
    Isochronous in Endpoint
    487
  - Isochronous in Transactions
    488
    
    Bulk and Interrupt out Endpoint
    488
  - Bulk and Interrupt out Transactions
    490
    
    Isochronous out Endpoint
    490
  - Isochronous out Transactions
    492
    
    Dma
    492
    
    Remote Wake-Up
    492
  - USB Register Summary
    493
    
    USB Registers
    493
    
    USB Registers Overview
    493
    
    USB Register Descriptions
    494
  - Security Core
    508
    
    PKA Engine
    509
    
    Overview
    510
  - Summary of PKCP Vector Operations
    511
    
    Functional Description
    511
  - Pka_Compare
    512
  - PKCP Result Vector Memory Allocation
    512
  - Restrictions on Input Vectors for PKCP Operations
    512
  - PKCP Result Vector / Input Vector Overlap Restrictions
    513
  - Summary of Expmod Operations
    513
    
    Sequencer Operations
    513
  - Restrictions on Input Vectors for Expmod Operations
    514
  - Expmod Result Vector/Scratchpad Area Memory Allocation
    515
  - Expmod Scratchpad Area / Input Vector Overlap Restrictions
    515
    
    PKA RAM Size Needed for Exponentiation Operations
    515
  - Maximum Number of Odd Powers for 2K Byte PKA RAM Size
    516
  - Pka_Dptr
    516
    
    Modular Inversion Operation
    516
  - Required PKA RAM Sizes for Exponentiations
    516
  - Summary of Modinv Operation
    516
  - Modinv Result Vector/Scratchpad Area Memory Allocation
    517
  - Modinv Scratchpad Area / Input Vector Overlap Restrictions
    517
  - Operational Restrictions on Input Vectors for the Modinv Operation
    517
  - Pka_Shift
    517
    
    Modular Inversion with an Even Modulus
    517
  - PKA_SHIFT Result Values for Modinv Operation
    517
  - PKA_SHIFT Result Values for ECC Operations
    518
    
    Modular Inversion with a Prime Modulus
    518
  - Summary of ECC Operations
    518
  - Basic PKCP Operations Performance
    519
  - ECC Result Vector/Scratchpad Area Memory Allocation
    519
  - ECC Scratchpad Area / Input Vector Overlap Restrictions
    519
  - Operational Restrictions on Input Vectors for ECC Operations
    519
  - Exponentiation Performance for 16-Bit PKCP-Only
    520
    
    Expmod Performance
    520
  - ECC-ADD Performance
    522
    
    Modular Inversion Performance
    522
  - Modinv Performance
    522
  - ECC-MUL Performance
    523
    
    Interfaces
    523
  - Pka_Aptr
    524
  - Pka_Bptr
    524
  - Pka_Cptr
    524
    
    PKA Vector_B Address (PKA_BPTR)
    524
  - Pka_Alength
    525
    
    PKA Vector_D Address (PKA_DPTR)
    525
  - Pka_Blength
    526
  - Pka_Function
    526
    
    PKA Bit Shift Value (PKA_SHIFT)
    526
  - Pka_Divmsw
    527
    
    PKA Compare Result (PKA_COMPARE)
    527
  - Pka_Msw
    527
  - Pka_Ram
    528
    
    PKA Most-Significant-Word of Result Vector (PKA_MSW)
    528
  - Pka_Seq_Ctrl
    529
    
    PKA Sequencer Control/Status Register (PKA_SEQ_CTRL)
    529
  - Pka_Options
    530
  - Pka_Sw_Rev
    530
    
    PKA HW Options Register (PKA_OPTIONS)
    530
  - Pka_Revision
    531
    
    PKA HW Revision Register (PKA_REVISION)
    531
    
    PKA Vector Ram (PKA_RAM)
    532
  - Operation Sequences and Main Interrupt
    533
- Appendix A: RSA, ELGAMAL, DH, and DSA Use Cases
  
  534
  - A2: Diffie-Hellman Use Cases
    535
  - A4: DSA Use Cases
    536
  - AES and SHA Cryptoprocessor
    537
    
    Master Control and Interrupts
    538
    
    Master Bus
    539
  - Register Names and Detail
    540
  - DMA Controller and Its Integration
    542
  - DMAC Channel Control Register
    544
    
    Channels and Arbiter
    544
  - Supported DMAC Operations
    544
  - DMAC Channel External Address
    545
  - DMAC Channel Length
    545
  - DMAC Software Reset
    546
    
    Control/Status Registers
    546
  - DMAC Status
    546
  - DMAC Master Run-Time Parameters
    547
  - DMAC Options Register
    548
  - DMAC Port Error Raw Status
    548
  - DMAC Version Register
    549
    
    Master Control and Select
    549
  - Master Control Algorithm Select (CTRL_ALG_SEL)
    550
  - Master Control Algorithm Select
    551
  - Software Reset
    551
    
    Master PROT Enable
    551
  - Valid Combinations for CTRL_ALG_SEL Flags
    551
  - Interrupt Configuration
    552
  - Interrupt Clear
    553
  - Interrupt Set
    554
  - Interrupt Status
    555
    
    Version and Configuration Registers
    555
  - Options Register
    556
  - Version Register
    556
    
    AES Engine
    557
  - Aes_Key
    558
  - Key Registers Used Per Key Size
    559
  - Table 39AES Initialization Vector Registers
    559
  - AES Input/Output Control and Mode Register
    560
  - Crypto Data Length Register (LSW)
    563
  - Crypto Data Length Register (MSW)
    563
    
    AES Crypto Length Registers
    563
  - Authentication Length Register
    564
  - Data Input/Output Register
    565
  - AES Tag Output Register
    566
    
    TAG Registers
    566
  - Input/Output Block Format Per Operating Mode
    566
  - Hash Data Input Register
    567
    
    HASH Core
    567
  - Hash I/O Buffer Control
    568
    
    Input/Output Buffer Control & Status Register
    568
  - Hash Mode Register
    571
    
    Mode Registers
    571
  - Hash Length Register
    572
    
    Length Registers
    572
    
    Hash Digest Registers
    573
  - Key Store Write Area Register
    574
  - Key Store Written Area (Status) Register
    574
  - Key Store Size Register
    575
  - Key Store Read Area Register
    576
  - Performance
    576
  - Performance Table for DMA-Based Operations
    577
    
    Programming Guidelines
    578
    
    Interrupting DMA Transfers
    579
    
    Data Format and Byte Order
    580
    
    Hmac
    582
  - Symmetric Crypto Processing Steps
    577
  - Implementation of Secure HMAC Operation
    583
    
    Alternative Basic Hash Where Data Originates from the Slave Interface
    584
  - Aes_Key
    586
    
    Encryption/Decryption
    586
    
    Basic AES Modes
    587
    
    Aes-Gcm
    589
    
    Cbc-Mac
    590
    
    Aes-CCM
    591
    
    Exceptions Handling
    593
    
    Conventions and Compliances
    594
    
    Terminology
    595
  - Mapping of Internal Address Bus to the External Address Bus
    596
    
    Register Information
    596
  - Pkp_Options
    597
    
    Register Description
    597
    
    Advanced Interrupt Controller (Optional)
    598
  - Pkp_Revision
    597
  - AIC: Functional Logic of One Interrupt Source
    599
  - PKP Interrupt Sources
    599
  - Aic_Pol_Ctrl
    600
    
    AIC Registers
    600
  - Aic_Enable_Ctrl
    601
    
    AIC Enable Control Register (AIC_ENABLE_CTRL)
    601
  - Aic_Type_Ctrl
    601
  - Aic_Ack
    602
  - Aic_Enabled_Stat
    602
  - Aic_Raw_Stat
    602
  - Aic_Enable_Clr
    603
  - Aic_Enable_Set
    603
  - Aic_Options
    604
  - Aic_Version
    604
  - AES Register Summary
    605
    
    AES and PKA Registers
    605
    
    AES Register Descriptions
    608
  - Hash Digest Registers
    648
    
    PKA Registers
    657
  - PKA Register Summary
    658
    
    PKA Register Descriptions
    658
  - Pka_Program
    665
    
    Radio
    668
    
    RF Core
    669
  - Interrupt Registers Register Map
    670
    
    FIFO Access
    670
  - Frame Filtering and Source Matching Memory Map
    671
    
    Frequency and Channel Programming
    672
  - IEEE 802.15.4-2006 Symbol-To-Chip Mapping
    673
    
    IEEE 802.15.4-2006 Modulation Format
    673
  - I and Q Phases When Transmitting a Zero-Symbol Chip Sequence, T
    674
  - Schematic View of the IEEE 802.15.4 Frame Format
    674
    
    IEEE 802.15.4-2006 Frame Format
    674
  - Format of the Frame Control Field (FCF)
    675
    
    MAC Layer
    675
  - Frame Data Written to the TX FIFO
    676
    
    TX State Timing
    676
    
    TX Flow Diagram
    677
  - TX Flow
    678
  - Transmitted Synchronization Header
    679
    
    Frame Processing
    679
  - FCS Hardware Implementation
    680
    
    Interrupts
    680
    
    RX State Timing
    681
  - SFD Signal Timing
    682
    
    Frame Filtering
    682
    
    Interrupts
    683
  - Filtering Scenarios (Exceptions Generated During Reception)
    684
    
    Tips and Tricks
    684
    
    Source Address Matching
    685
  - Matching Algorithm for Short and Extended Addresses
    686
    
    Address Enable Registers
    686
  - Interrupts Generated by Source Address Matching
    687
  - Acknowledge Frame Format
    688
    
    Frame-Check Sequence
    688
  - Data in RX FIFO for Different Settings
    688
  - Acknowledgement Timing
    689
  - Command Strobe Timing
    689
    
    Transmission Timing
    689
    
    Automatic Setting of the Frame Pending Field (AUTOPEND)
    690
  - Behavior of FIFO and FIFOP Signals
    691
    
    Error Conditions
    691
    
    Link Quality Indication
    692
  - FSM State Mapping
    693
  - Main FSM
    693
  - FFT of the Random Bytes
    694
    
    Random Number Generation
    694
  - Histogram of 20 Million Bytes Generated with the RANDOM Instruction
    695
    
    Packet Sniffing and Radio Test Output Signals
    695
    
    Command Strobe/Csma-CA Processor
    696
    
    Program Execution
    697
  - CSP Registers Register Map
    698
  - Running a CSP Program
    698
  - Instruction Set Summary
    699
    
    Instruction Set Definition
    700
    
    Decy
    701
    
    Incmaxy
    702
    
    Setcmp1
    703
    
    Wevent2
    704
    
    Skip S, C
    705
    
    Snop
    706
    
    Ssamplecca
    707
    
    Sackpend
    708
    
    Isstop
    709
    
    Isrxmaskbitclr
    710
    
    Isrfoff
    711
  - Registers that Require Update from Their Default Value
    712
    
    Isnack
    712
  - RFCORE_FFSM Register Summary
    713
    
    Radio Registers
    713
    
    RFCORE_FFSM Register Descriptions
    714
  - RFCORE_XREG Register Summary
    721
    
    RFCORE_XREG Register Descriptions
    724
    
    RFCORE_SFR Registers
    760
    
    RFCORE_SFR Register Summary
    761
  - CCTEST Register Summary
    764
    
    ANA_REGS Registers
    768
  - ANA_REGS Register Summary
    769
    
    ANA_REGS Registers Mapping Summary
    769
  - Voltage Regulator
    770
    
    A.1 Smartrf™ Studio Software for Evaluation (Www.ti.com/Smartrfstudio)
    772
  - Additional Information
    777
    
    C.1 Texas Instruments Low-Power RF Web Site
    778
    
    E.1 Revision History – External
    780
    
    Important Notice
    781

Texas Instruments CC2538 Quick Start Manual (8 pages)

Evaluation Module Kit

Brand: Texas Instruments | Category: Motherboard | Size: 1 MB

Texas Instruments CC2538 Quick Start Manual (3 pages)

Evaluation Module Kit

Brand: Texas Instruments | Category: Motherboard | Size: 0 MB

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