Texas Instruments ThunderSWITCH II TNETX4090 User Manual
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Texas Instruments ThunderSWITCH II TNETX4090 User Manual

Texas Instruments ThunderSWITCH II TNETX4090 User Manual

9-port 100-/1000-mbit/s ethernet switch
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Single-Chip 100-/1000-Mbit/s Device
Integrated Physical Coding Sublayer (PCS)
Logic Provides Direct Interface to Gigabit
Transceivers
Integrated Address-Lookup Engine and
Table Memory for 2-K Addresses
Supports IEEE Std 802.1Q Virtual-LAN
(VLAN) Tagging Scheme
Provides Data Path for Network
Management Information [No External
Media-Access Control (MAC) Required]
Full-Duplex IEEE Std 802.3 Flow Control
Half-Duplex Back-Pressure Flow Control
Fully Nonblocking Architecture Using
High-Bandwidth Rambus Memory
Simple Expansion Via the Gigabit Interface
for Higher-Density Port Solutions

description

The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet
engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully
manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and
high-bandwidth rambus-based packet memory and a CPU. The TNETX4090 also provides an interface capable
of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units
(BPDU) (spanning tree) frames.
The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex
mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity. In
the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex
capability, ports 0–7 support 200-Mbit/s aggregate bandwidth connections. Port 8 supports 2 Gbit/s to desktops,
high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)
function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The
TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports
on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8
can be used to connect multiple devices in a ring topology, which provides a low-cost, high-port-density desktop
switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router
or crossbar switch to build a cost-effective, high-density, high-performance system.
The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and
up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
Ethernet and Etherstat are trademarks of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching .
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
POST OFFICE BOX 655303
SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999
Port Trunking/Load Sharing for
High-Bandwidth Interswitch Links
Supports Pretag Extended Port Awareness
EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)
Provides Direct Input/Output (DIO) Interface
for Configuration and Statistics Information
Supports On-Chip Per-Port Storage for
Etherstat
and Remote Monitoring (RMON)
Management Information Bases (MIBs)
Fabricated in 2.5-/3.3-V Low-Voltage
Technology
Supports Ring-Cascade Mode
Supports Spanning Tree
Packaged in 352-Terminal Ball Grid Array
Package
switch with an on-chip address-lookup
Copyright
DALLAS, TEXAS 75265
TNETX4090
1998, Texas Instruments Incorporated
1

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Summary of Contents for Texas Instruments ThunderSWITCH II TNETX4090

  • Page 1: Description

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
  • Page 2 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 description (continued) EEPROM 10/100 10/100 10/100 10/100 10/100 10/100 10/100 10/100 CPU I/F With Local Packet Switching Memory 100-M Management MDIO Switching Engine (Queue Manager) 100/1000 VLAN 802.1Q Hardware...

  • Page 3: Table Of Contents

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Contents Description ......... . . PCS Duplex LED .
  • Page 4 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 GGP PACKAGE (BOTTOM VIEW) POST OFFICE BOX 655303 DALLAS, TEXAS 75265...

  • Page 5: Spws044E – December 1997 – Revised August

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL NAME NAME NAME NAME NAME AF26 DBUS_CTL M03_CRS M06_RXD2 MDIO...
  • Page 6 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued) SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL NAME NAME NAME NAME NAME AF24 RESET SDMA V DD(2.5)

  • Page 7: Terminal Functions

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions JTAG interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR † NAME Test clock. Clocks state information and test data into and out of the TNETX4090 during operation Pullup TCLK of the test port.

  • Page 8: Post Office Box 655303 Dallas, Texas

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface (GMII mode) TERMINAL INTERNAL DESCRIPTION RESISTOR † NAME Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision. Pulldown Additionally, during full-duplex operation, transmission of new frames does not commence if this M08_COL...
  • Page 9 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode] TERMINAL INTERNAL DESCRIPTION NAME RESISTOR Receive byte clock 1. M08_COL is used to input receive byte clock 1 from the attached SERDES Pulldown M08_COL device.
  • Page 10 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] TERMINAL INTERNAL DESCRIPTION NAME RESISTOR Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision. Pulldown Additionally, during full-duplex operation, transmission of new frames does not commence if this M08_COL...
  • Page 11 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued) TERMINAL INTERNAL DESCRIPTION NAME RESISTOR Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD3–M08_TXD0. This signal None M08_TXEN is synchronous to M08_RFCLK.
  • Page 12 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME M00_RENEG M01_RENEG M02_RENEG Renegotiate. Indicates to the attached PHY device that this port wishes to renegotiate a new M03_RENEG None configuration.
  • Page 13 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME M00_RXER M01_RXER M02_RXER M03_RXER Pulldown Receive error. Indicates reception of a coding error on received data. M04_RXER M05_RXER M06_RXER...
  • Page 14 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME M00_TXEN M01_TXEN M02_TXEN Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to M03_TXEN None Mxx_TCLK.

  • Page 15: Rdram Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) RDRAM interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME Bus control. Controls signal-to-frame packets, transmits part of the operation code, None initiates data transfers, and terminates data transfers. This is a rambus signal logic (RSL) DBUS_CTL signal (see Note 1).

  • Page 16: Dio Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) DIO interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME SAD0 AF22 DIO address bus. Selects the internal host registers provided SDMA is high. Internal pullup Pullup SAD1 AE22...

  • Page 17: Led Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Terminal Functions (Continued) LED interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME AD19 None LED clock. Serial shift clock for the LED status data. LED_CLK AE19 None LED data.

  • Page 18: Dio Interface Description

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description The DIO is a general-purpose interface that is used with a range of microprocessor or computer system interfaces. The interface is backward compatible with the existing TI ThunderSWITCH products.
  • Page 19 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS SysControl StatControl 0x00F8 Reserved (for EEPROM CRC) 0x00FC VLAN0Ports 0x0100 VLAN1Ports...
  • Page 20 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS VLAN40Ports 0x01A0 VLAN41Ports 0x01A4 VLAN42Ports 0x01A8 VLAN43Ports 0x01AC VLAN44Ports 0x01B0 VLAN45Ports...
  • Page 21 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS VLAN37QID VLAN36QID 0x0348 VLAN39QID VLAN38QID 0x034C VLAN41QID VLAN40QID 0x0350 VLAN43QID VLAN42QID...
  • Page 22 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS XMultiGroup19 0x054C XMultiGroup20 0x0550 XMultiGroup21 0x0554 XMultiGroup22 0x0558 XMultiGroup23 0x055C XMultiGroup24...
  • Page 23 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS XMultiGroup61 0x05F4 XMultiGroup62 0x05F8 XMultiGroup63 0x05FC Reserved 0x0600–0x060C PCS8Status PCS8Control 0x0700...
  • Page 24 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description (continued) Table 3 and Table 4 list the least significant byte address for the port-specific statistics. Each statistic is four bytes long. To determine the address of a particular statistic, replace the xx in the head column with the characters from the tail address.
  • Page 25 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 3. Port Statistics 1 TAIL PORT NO. HEAD STATISTIC EVEN PORTS PORTS 0x80xx Receive octet 0x80xx Good receive frames 0x81xx Broadcast receive frames 0x81xx Multicast receive frames 0x82xx Receive CRC errors...
  • Page 26 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 4. Port Statistics 2 TAIL PORT NO. HEAD STATISTIC (ALL PORTS) Pause transmit frames † 0x900x Pause receive frames † 0x901x 0x902x Security violations 0x903x Reserved 0x904x...

  • Page 27: Receiving/Transmitting Management Frames

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface description (continued) Table 5. Address-Lookup Statistics PORT NO. HEAD STATISTIC 0x9200–0x9FFC Reserved 0xA000 Unknown unicast destination addresses 0xA004 Unknown multicast destination addresses 0xA008 Unknown source addresses 0xA00C–0xFFFC Reserved...

  • Page 28: State Of Dio Signal Terminals During Hardware Reset

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 state of DIO signal terminals during hardware reset The CPU can perform a hardware reset by writing to an address in the range of 0x40–0x5F (writes to a DMA address in this range have no effect on reset);...
  • Page 29 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame format on the NM port (continued) To provide a CRC word, which includes the header, the NM port generates a new CRC word as the frame is being read out.
  • Page 30 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame format on the NM port (continued) Any device reading frames out of the NM port must expect frames to be in the format shown in Figure 2. Frames received into the switch on the NM port also must conform to this format, with the following caveats: crc = 0 in NMRxControl When the host is providing a frame containing valid CRC it also must provide in the TPID field valid header...

  • Page 31: Full-Duplex Nm Port

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 full-duplex NM port The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e., read or write) that determines whether a byte is removed from the transmit queue or added to the receive queue. The DIO interface, however, is only half duplex since it cannot do a read and write at the same time.

  • Page 32: Mac Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MAC interface receive control Data received from the PHYs is interpreted and assembled into the TNETX4090 buffer memory. Interpretation involves detection and removal of the preamble, extraction of the address and frame length, extraction of the IEEE Std 802.1Q header (if present), and data handling and CRC.

  • Page 33: Adaptive Performance Optimization (Apo)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 adaptive performance optimization (APO) Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled, the MAC uses transmission pacing to enhance performance (when connected on networks using other transmit pacing-capable MACs).

  • Page 34: 100-Mbit/S Mii (Ports 0-7)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 10-/100-Mbit/s MII (ports 0–7) speed, duplex, and flow-control negotiation Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indicate (or not) support of IEEE Std 802.3 flow control.
  • Page 35 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 TXCLK TXEN TXER Î Î Î Î Reserved Reserved TXD3 Î Î Î Î Î Î Î Î Î Î Î Î Reserved Speed TXD2 Î...

  • Page 36: 1000-Mbit/S Phy Interface (Port 8)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 100-/1000-Mbit/s PHY interface (port 8) This port is controlled by an IEEE Std 802.3-compliant MAC. speed, duplex, and flow-control negotiation When in PMA mode and autonegotiation is enabled, the on-chip PCS layer attempts to establish a compatible mode of operation with the attached serializer/deserializer (SERDES).

  • Page 37: Full-Duplex Hardware Flow Control

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 speed, duplex, and flow-control negotiation (continued) In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain inputs, to allow the port to negotiate with the PHY device for duplex and IEEE Std 802.3 pause frame support at power up via the EEPROM contents.

  • Page 38: Pretagging And Extended Port Awareness

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 pretagging and extended port awareness The TNETX4090 can be incorporated into a hierarchical system, whereby this port is connected to a crossbar matrix with up to 17 1000-Mbit/s ports. By making this TNETX4090 aware of the ports on the crossbar matrix, the crossbar matrix does not need to make any forwarding or filtering decisions, and can be relatively inexpensive.
  • Page 39 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 10. Transmit Pretag Bit Definitions NAME FUNCTION 31–28 reserved Reserved. These bits always are 0. Receive header. Indicates whether an IEEE Std 802.1Q header was added to the frame on reception. rxheader –...

  • Page 40: Ring-Cascade Topology

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 12. Directed Format Receive Pretag Bit Definitions NAME FUNCTION One. Indicates directed format. The frame is routed to port(s) specified in portvector that are enabled (disabled in portxcontrol = 0), regardless of whether the destination address is unicast or multicast (i.e., the destination address is not examined).
  • Page 41 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 ring-cascade topology (continued) Frames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV is asserted. The contents of the pretag are examined, and based on the results, are either forwarded normally, or immediately discarded within the MAC.

  • Page 42: Eeprom Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfigured system. This also can be used to change or reconfigure the system and retain the preferences between system power downs.

  • Page 43: Interaction Of Eeprom Load With The Sio Register

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface (continued) After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues for the 24C02 EEPROM.

  • Page 44: Compatibility With Future Device Revisions

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 compatibility with future device revisions All EEPROM locations that correspond to reserved addresses in the memory map, register bits that are read only, and register bits that are marked as reserved should be set to 0 to ensure compatibility with future versions of the device.

  • Page 45: Lamp Test

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Table 17. LED Status Bit Definitions and Shift Order ORDER NAME NAME FUNCTION FUNCTION slast = 0 slast = 1 Software LEDs 0–11. These allow additional software-controlled status to be displayed. These 12 LEDs reflect the values of bits 0–11 of the swied field in LEDControl at the moment that the LED 1st–12th 11th–22nd...
  • Page 46 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 TNETX4090 V CC V REF TXCLK V DD RXCLK Concurrent BUS ENABLE RDRAM BUS CTRL S IN S OUT BUS DATA (8–0) SCHAIN0 TXCLK V REF V DD RXCLK Concurrent...

  • Page 47: Jtag Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 JTAG interface The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones. The instructions that TI supports are: Mandatory (EXTEST, BYPASS, and SAMPLE/PRELOAD) Optional public (HIGHZ, IDCODE, and BIST) Private (various private instructions are used by TI for test purposes)

  • Page 48: Frame Routing

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 frame routing VLAN support The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 11 and described in the following paragraphs. Receive Record IEEE Std...

  • Page 49: Address Maintenance

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 IEEE Std 802.1Q tags – reception By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after the source address).
  • Page 50 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 aging algorithms time-threshold aging When learning addresses, the IALE adds the address to the table and tags it with a time stamp. If another frame is received with this address, the time stamp is refreshed.
  • Page 51 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Start Key: UnkVLAN Known interrupt VLAN? statistic Unkmem Source Port = 1 in. VLANnPorts? Destination Address Found? Destination Destination Destination Destination Locked Bit = 1? Multicast? Multicast? Multicast?
  • Page 52 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Source Source Port = 1 in Address NLearnPorts? Found? Source Locked Bit = 1? Source AND UnkSrcPorts Port With VLAN Moved? VLANnPorts, Then OR With Port Routing Code Unknown secvio...
  • Page 53 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 Remove: – Disabled Ports – Ports Blocked by TxBlockPorts From Port Routing Code [(Source Port = MirrorPort or Mirr Port Routing Code Includes MirrorPort) Bit = 1? and (Source Port ! = UplinkPort)] Then Include UplinkPort in Port Routing Code...

  • Page 54: Port Trunking/Load Sharing

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 removal of source port Normally, the IALE does not route a frame to a port on which it was received. The port routing code is examined to see if the source port is included.

  • Page 55: Port-Trunking Example

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 port trunking example This example shows how to set up the TNETX4090 to support two port trunks. The first trunk group consists of ports 1, 3, 5, and 7 (see Table 21); the second trunk group consists of ports 0, 2, and 6 (see Table 22). Table 21.

  • Page 56: Flow Control

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 flow control The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flow control for ports in full-duplex mode. The flow bit in the SysControl register determines the action that will be taken when back pressure is needed, that is, when there are insufficient resources to handle an inbound packet.

  • Page 57: Other Flow-Control Mechanisms

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 other flow-control mechanisms hardware flow control If a port were in MII or GMII mode and full duplex, normally, its Mxx_COL would not be needed. Hardware flow control has been added by preventing the start of a frame transmission if the Mxx_COL is high.

  • Page 58: Reading Rdram

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 reading RDRAM Reading from RDRAM memory is accomplished as follows: 1. Write the byte address for the access to ramaddress in RAMAddress. 2. Set rdwrite = 1 and rdram = 1 (these can be written simultaneously). 3.

  • Page 59: Duplex Wrap Test

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 internal wrap test (continued) TNETX4090 Figure 13. Internal Wrap Example The operational status of the PHYs or external connections to the device do not have to be considered or assumed good, when in internal loopback mode.

  • Page 60: Absolute Maximum Ratings

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 † absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V (see Note 1) ......... –0.5 V to 2.7 V DD(2.5) Supply voltage range, V...

  • Page 61: Electrical Characteristics

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT V OH High-level output voltage I OH = rated V DD(3.3) –0.5 V OL Low-level output voltage I OL = rated...

  • Page 62: Physical Medium Attachment Interface (Port 8)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 physical medium attachment interface (port 8) receive PMA receive (see Figure 16) UNIT t c(Mxx_RBC) Cycle time, receive byte clock 0 and 1 (Mxx_RCLK, Mxx_COL) Drift rate †...

  • Page 63: Transmit

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 transmit PMA transmit (see Figure 17) UNIT 8 † 8 † t c(Mxx_GTCLK) Cycle time, Mxx_GTCLK t w(Mxx_GTCLK) Pulse duration, Mxx_GTCLK low or high t c(Mxx_GTCLK) t su(Mxx_TXD) Setup time, Mxx_RXD7–Mxx_RXD0 valid before Mxx_GTCLK t su(Mxx_TXEN)

  • Page 64: Gmii (Port 8)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 GMII (port 8) Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s. Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD7–MxxRXD0 is driven by the PHY on the falling edge of Mxx_RCLK.
  • Page 65 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PMA and GMII clock (see Figure 20) UNIT t r(Mxx_GCLK) Pulse width low, Mxx_RFCLK t h(Mxx_GCLK) Pulse width high, Mxx_RFCLK t w(Mxx_GCLK) Cycle time, Mxx_RFCLK PMA and GMII clock (see Figure 20) UNIT t r(Mxx_GCLK)

  • Page 66: Mii (Ports 0-8)

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MII (ports 0–8) Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII operating at 100-Mbit/s. Mxx_CRS and Mxx_COL are driven asynchronously by the PHY. Mxx_RXD3–Mxx_RXD0 is driven by the PHY on the falling edge of Mxx_RCLK.
  • Page 67 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MII transmit (see Figure 22) UNIT t d(Mxx_TXD) Delay time, from Mxx_TCLK to Mxx_TXD3–MxxTXD0 valid t d(Mxx_TXEN) Delay time, from Mxx_TCLK to Mxx_TXEN valid t d(Mxx_TXER) Delay time, from Mxx_TCLK to Mxx_TXER valid Mxx_TCLK Î...

  • Page 68: Rdram Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 RDRAM interface RDRAM (see Figure 24) UNIT t c(DX_CLK) Cycle time DTX_CLK, DRX_CLK 3.33 3.33 2, 3 t w(DX_CLK) Pulse duration, DTX_CLK, DRX_CLK low or high t c(DX_CLK) 4, 5 t w(TICK)

  • Page 69: Dio Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO interface The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces. DIO and DMA writes (see Figure 25) UNIT t w(SCS) Pulse duration, SCS...
  • Page 70 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 DIO and DMA reads (see Figure 26) UNIT t w(SCSL) Pulse duration, SCS low 2t c t su(SRNW) Setup time, SRNW valid before SCS t su(SAD) Setup time, SAD1–SAD0, SDMA valid before SCS t h(SRNW) Hold time, SRNW low after SRDY...

  • Page 71: Eeprom Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 EEPROM interface For further information on EEPROM interface timing, refer to the 24C02 or 24C08 serial EEPROM data sheets. EEPROM writes (see Figure 27) UNIT t su(EDIO:Start) Setup time, start condition during ECLK high t h(EDIO:Start)

  • Page 72: Led Interface

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 LED interface LED (see Figure 29) UNIT t c(LED_CLK) Cycle time, LED_CLK t w(LED_CLK) Pulse duration, LED_CLK high 24 † t n(LED_CLK) Number of LED_CLK pulses in burst 4687488 ‡...

  • Page 73: Parameter Measurement Information

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION The following load circuits and voltage waveforms show the conditions used for measuring switching characteristics. Test points are illustrated schematically on the load circuits. Reference points are plotted on the voltage waveforms. IV110 From Output Under Test...
  • Page 74 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION V DD Input t PHL V OH Out-of-Phase Output V OL t PHL t PLH t PHL V OH In-Phase Output V OL Figure 33.
  • Page 75 TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION Hi-Z Input V DD (active-low Active enable) t PZH V OH Output 50% LVCMOS High 1.3 V TTL Hi-Z (forced low) t PZL Hi-Z (forced high) Output 50% LVCMOS...

  • Page 76: Mechanical Data

    TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) PACKAGE 31,75 SQ 35,20 1,27 34, 80 26 24 22 20 16 14 Heat Slug 1,70 MAX 0,91 NOM Seating Plane...
  • Page 77 PACKAGE OPTION ADDENDUM www.ti.com 4-May-2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Type Drawing TNETX4090GGP OBSOLETE Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

  • Page 78: Important Notice

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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