Texas Instruments ThunderSWITCH TNETX3270 Manual
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Texas Instruments ThunderSWITCH TNETX3270 Manual

Texas Instruments ThunderSWITCH TNETX3270 Manual

24/3 ethernet switch with 24 10-mbit/s ports and 3 10-/100-mbit/s ports
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D
Port Configurations:
Twenty-Four 10-Mbit/s Ports
– Ports Arranged in Three Groups of Eight
Ports in a Multiplexed Interface
– Direct Multiplexer Interface to
TNETE2008
– Full and Half Duplex
– Half-Duplex Collision-Based Flow
Control
– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE
Std 802.1Q VLAN
– Speed, Duplex, and Pause
Autonegotiation With Physical Layer
(PHY)
Three 10-/100-Mbit/s Ports
– Direct Interface to TNETE2101
– Full and Half Duplex
– Half-Duplex Collision-Based Flow
Control
– Full-Duplex IEEE Std 802.3x Flow Control
– Interoperable Support for IEEE
Std 802.1Q VLAN
– Pretagging Support
D
Port Trunking and Load Sharing
D
LED Indication of Port Status
D
SDRAM Interface
– Direct Interface to 8-Bit/Word and
16-Bit/Word, 16-Mbit, and 64-Mbit
SDRAMs
– 32-Bit-Wide Data Bus
SDRAM
Controller
EEPROM
Interface
CPU
Interface
Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.
Ethernet is a trademark of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching .
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
TAP
(JTAG)
Queue
Manager
Network
Statistics
Logic
Statistics
Storage
MIB
LED
Address
Compare
POST OFFICE BOX 655303
ThunderSWITCH 24/3 ETHERNET SWITCH
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
– Up to 32 Mbytes Supported
– 83.33-MHz SDRAM Clock
– 12-ns (–12) SDRAMs Required
D
Remote Monitoring (RMON) Support –
Groups 1, 2, 3, and 9
D
Direct I/O (DIO) Management Interface
– Eight Bits Wide
– CPU Access to Statistics, Registers, and
Management Information Bases (MIBs)
– Internal Network Management Port
– Forwards Spanning-Tree Packets to CPU
– Serial Media-Independent Interface (MII)
for PHY Control
D
EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)
D
Internal Address-Lookup/Frame-Routing
Engine
– Interoperable Support for IEEE
Std 802.1Q VLAN
– Supports IEEE Std 802.1D Spanning Tree
– Thirty-Two Assignable Virtual LANs
(VLANs)
– Multiple Forwarding Modes
– 2K Total Addresses Supported
– Port Mirroring
D
IEEE Std 1149.1 (JTAG) Interface (3.3-V
Signals)
D
2.5-V Process With 3.3-V-Drive I/O
D
Packaged in 240-Terminal Plastic Quad
Flatpack
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
Controller (MAC)
MII
Controller (MAC)
Controller (MAC)
MII
Controller (MAC)
MII
Copyright
DALLAS, TEXAS 75265
TNETX3270
Eight Ports
(00–07)
10 Mbit/s
Eight Ports
(08–15)
10 Mbit/s
Eight Ports
(16–23)
10 Mbit/s
Three Ports
(24–26)
10/100 Mbit/s
1999, Texas Instruments Incorporated
1

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Summary of Contents for Texas Instruments ThunderSWITCH TNETX3270

  • Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.

  • Page 2: Description

    The TNETX3270 provides highly integrated switching solutions that allow network designers to lower overall system costs. Based on Texas Instruments (TI ) ThunderSWITCH architecture, the TNETX3270 design integrates 24 full-duplex 10-Mbit/s ports and 3 full-duplex 10-/100-Mbit/s ports, as well as an address-lookup engine, all in a single 240-pin package.

  • Page 3: Table Of Contents

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Contents Description ......... . . SDRAM Interface .

  • Page 4: Pgv Package Terminal Layout

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 PGV PACKAGE (TOP VIEW) DD26 MDIO DD27 MRESET DD28 DD(2.5V) ECLK DD(2.5V) DD29 EDIO DD30 RESET DD31 LEDDATA LEDCLK DCAS OSCIN DRAS...

  • Page 5: Tnetx3270 Interface Block Diagram

    TH0CLK TRST Controller (MAC) Controller (MAC) TH0TXD3–TH0TXD0 JTAG Controller (MAC) Controller (MAC) TH0TXEN Test Access TCLK Controller (MAC) TH0COL Port (TAP) Eight Ports Controller (MAC) TH0CRS (00–07) Controller (MAC) TH0SYNC 10 Mbit/s TH0RXD3–TH0RXD0 Controller (MAC) DD31–DD0 TH0RXDV Controller (MAC) DA12–DA0 TH0LINK DRAM Controller (MAC)

  • Page 6: Terminal Functions

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions 10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, TH1, and † TH2) of eight ports TERMINAL INTERNAL DESCRIPTION...
  • Page 7 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) 10-Mbit/s MAC multiplexed interface (ports 00–23) is multiplexed into three groups (TH0, TH1, and † TH2) of eight ports (continued) TERMINAL INTERNAL...
  • Page 8 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) † 10-/100-Mbit/s MAC interface (ports 24–26) (continued) TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME M24RXD3 M24RXD2 M24RXD1 M24RXD0 M25RXD3 Receive data (nibble receive data from the attached PHY or PMI device).
  • Page 9 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) SDRAM interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME DA13 DA12 DA11 DA10 DA09 DA08 SDRAM address bus (time-multiplexed bank, row, and column address). The address bus DA07 None DA13–DA00 also provides the SDRAM mode register initialization value.
  • Page 10 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) host DIO interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME SAD1 Pullup DIO address bus. SAD1 and SAD0 select the internal host registers, when SDMA is high. SAD0 Pullup DIO chip select.
  • Page 11 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) serial MII management PHY interface TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME Serial MII management data clock. MDCLK can be disabled (high impedance) through the O/High Z Pullup MDCLK...
  • Page 12 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Terminal Functions (Continued) miscellaneous TERMINAL INTERNAL DESCRIPTION DESCRIPTION RESISTOR NAME None Master system clock input (83.33-MHz input clock) OSCIN None Reset.

  • Page 13: Dio Register Groups

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 DIO register groups Table 1. Internal Register and Statistics Memory Map LOADABLE LOADABLE REGISTERS USING 24C02 USING 24C08 ADDRESS EEPROM? EEPROM? RANGE...
  • Page 14 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 2. Detailed DIO Register Map BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS Port1control Port0control 0x0000 Port3control Port2control 0x0004 Port5control...
  • Page 15 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 2. Detailed DIO Register Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS Reserved (for EEPROM CRC) 0x00FC VLAN0ports 0x0100...
  • Page 16 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 2. Detailed DIO Register Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS VLAN17QID VLAN16QID 0x0320 VLAN19QID VLAN18QID 0x0324...
  • Page 17 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 2. Detailed DIO Register Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 ADDRESS Findnode<23–16> Findnode<31–24> Findnode<39–32> Findnode<47–40>...

  • Page 18: Interface Description

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 interface description DIO interface The DIO interface is a general-purpose interface that can be used with a wide range of microprocessor or computer systems.

  • Page 19: Network Management Port

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 network management port Frames can be received or transmitted via the DIO interface using a built-in port, the network management (NM) port.
  • Page 20 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 frame format on the NM port The frame format on the NM port differs slightly from a standard Ethernet frame format. The key differences are: the frame always contains an IEEE Std 802.1Q header in the four bytes following the source address (see Figure 2).
  • Page 21 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 frame format on the NM port (continued) TPID (Tag Protocol Identifier) TCI (Tag Control Information) 1 0 0 0 0 0 0 0 0 0 0 0 Priority cfi VLAN ID 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0...

  • Page 22: Mii Serial Management Interface (Phy Management)

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 frame format on the NM port (continued) When a frame is transmitted on the NM port, no header stripping occurs (again because the NM port does not have a PortxQtag register or txacc bit), so the frame read by the host software contains one header (or possibly more, depending on how the frame was received).

  • Page 23: Receive Filtering Of Frames

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 receive filtering of frames Received frames that contain an error (e.g., CRC, alignment, jabber, etc.) are discarded before transmission and the relevant statistics counter is updated.

  • Page 24: Receive Versus Transmit Priority

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 receive versus transmit priority The queue manager prioritizes receive and transmit traffic as follows: Highest priority is given to frames that currently are being transmitted. This ensures that transmitting frames do not underrun.

  • Page 25: Post Office Box 655303 Dallas, Texas

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 5. Source-Port Pretag Encoding MxxTXD3– MxxTXER SOURCE PORT MxxTXD0 0000 Port 00 0001 Port 01 0010 Port 02 0011 Port 03 0100...
  • Page 26 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 port-routing-code pretag on reception If the pretag bit is set to 1 in the appropriate Portxcontrol register, during the seven MxxRCLK cycles prior to MxxRXDV going high, the port expects to receive a seven-nibble pretag on MxxRXD3–MxxRXD0 (see Figure 4).

  • Page 27: Eeprom Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 EEPROM interface The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less, preconfigured system to their customers. Customers also may want to change or reconfigure their system and retain their preferences between system power downs.

  • Page 28: Interaction Of Eeprom Load With The Sio Register

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 EEPROM interface (continued) Multiple bus masters are not supported on the EEPROM interface because the ECLK pin always is driven by the device with a strong 0/strong 1 (i.e., not a strong 1/resistively pulled-up 1).

  • Page 29: Jtag Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 JTAG interface The TNETX3270 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones.

  • Page 30: Lamp Test

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 10. LED Status Bit Definitions and Shift Order ORDER NAME NAME FUNCTION FUNCTION slast = 0 slast = 1 1–7 1–7 Zero.
  • Page 31 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Table 11. 10-Mbit/s Interface Connections TNETX3270 TNETE2008 TERMINAL TERMINAL THxCLK IFCLK THxSYNC IFSYNC THxCOL IFCOL THxCRS IFCRS THxLINK IFLINK THxRXD3 IFRXD3 THxRXD2...
  • Page 32 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 PORT SYNC TXD3- M00TXD M01TXD M02TXD M03TXD M04TXD M05TXD M06TXD M07TXD M00TXD M01TXD TXD0 TXEN M00TXEN M01TXEN M02TXEN M03TXEN M04TXEN M05TXEN M06TXEN M07TXEN M00TXEN M01TXEN FORCEHD M00FHD M01FHD...
  • Page 33 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 THxCLK Clock Runs Continuously (input) THxTXEN (output) THxTXD3 Must be 0 (output) THxTXD2 Must be 0 (output) THxTXD1 Pause (0 = no pause) (1 = pause requested) (output) THxTXD0...

  • Page 34: 100-Mbit/S Mac Interfaces (Ports 24-26)

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 10-/100-Mbit/s MAC interfaces (ports 24–26) Unlike the 10-Mbit/s ports, each 10-/100-Mbit/s port has a dedicated set of signals to interface to its PHY. Table 12 shows how a TNETE2101 10-/100-Mbit/s PHY would be connected to one of the 10-/100-Mbit/s ports of TNETX3270.

  • Page 35: 10-/100-Mbit/S Port Configuration In A Nonmanaged Switch

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 10-/100-Mbit/s port configuration (continued) Each terminal is considered to be bidirectional, when pulled low by either TNETX3270 or by the PHY (or other external connections).

  • Page 36: 10-/100-Mbit/S Port Configuration In A Managed Switch

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 10-/100-Mbit/s port configuration in a managed switch The 10-/100-Mbit/s ports can be configured in a managed switch using either of the following procedures: 1.
  • Page 37 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 SDRAM interface (continued) Table 15. TNETX3270 Terminal Interface to SDRAMs TERMINALS SDRAM TERMINAL FUNCTION SDRAM TERMINAL FUNCTION TNETX3270 SDRAM DA13 Row/bank address (64-M SDRAMs only) DA12...

  • Page 38: Sdram-Type And Quantity Indication

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 SDRAM-type and quantity indication Before beginning operation (by writing to the start bit of Syscontrol), it is necessary to indicate to the SDRAM interface whether 8 or 16 SDRAMs are being used.

  • Page 39: Frame Routing

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 frame routing VLAN support The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 8 and described in the following paragraphs.

  • Page 40: Ieee Std 802.1Q Headers - Reception

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 IEEE Std 802.1Q headers – reception When the internal address-lookup engine (IALE) examines the received frame, it contains an IEEE Std 802.1Q header (after the source address).

  • Page 41: Spanning-Tree Support

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 spanning-tree support Each port provides independent controls to block reception or transmission of frames, for learning of addresses, or to disable the port on a per-port basis. Blocking can be overridden to allow reception or transmission of spanning-tree frames.
  • Page 42 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Start Key: UnkVLAN Known interrupt VLAN? statistic Unkmem Source Port = 1 in. VLANnports? Destination Address Found? Destination Destination Destination Destination Locked...
  • Page 43 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Source Source Port = 1 in Address NLearnPorts? Found? Source Locked Bit = 1? Source AND UnkSrcPorts Port With VLAN Moved? VLANnports, Then OR With...

  • Page 44: Port Mirroring

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 Remove: – Disabled Ports – Ports Blocked by TxBlockPorts From Port Routing Code ((Source Port = MirrorPort or Mirr Port Routing Code Includes MirrorPort) Bit = 1? and (Source Port ! = UplinkPort))

  • Page 45: Port Trunking/Load Sharing

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 port trunking/load sharing Port trunking is a technique that allows two or more ports to be parallel connected between switches and counted as one port to increase the bandwidth between those devices.

  • Page 46: Collision-Based Flow Control

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 collision-based flow control Collision-based flow control provides a means of preventing frame reception for ports that are operating in half-duplex mode.
  • Page 47 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 pause frame reception The IEEE Std 802.3X standard defines a MAC control frame as any frame containing a length/type value = 88.08 (hex).

  • Page 48: Internal Wrap Test

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 pause frame transmission (continued) Pause frames are transmitted if required, even if the port is observing the pausetime period from a pause frame it has received.

  • Page 49: Duplex Wrap Test

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 TNETX3270 Figure 10. Internal Wrap Example duplex wrap test Duplex wrap test is similar to internal wrap mode (see Figure 11). The ports can be set to accept frame data that is wrapped at the PHY.

  • Page 50: Port Mirroring

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 port mirroring It is possible to copy (or mirror) all frames that are received by and transmitted to a port designated by the Mirrorport register to the port designated by the Uplinkport register.

  • Page 51: Absolute Maximum Ratings

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 † absolute maximum ratings over operating junction temperature range (unless otherwise noted) Supply voltage range: V ........... –0.5 V to 2.7 V DD(2.5V) .

  • Page 52: Parameter Measurement Information

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION Outputs are driven to a minimum high-logic level of 3.3 V and to a maximum low-logic level of 0 V. Output transition times are specified as follows: For a high-to-low transition on either an input or output signal, the level at which the signal is said to be no longer high is 1.4 V and the level at which the signal is said to be low is 1.4 V.

  • Page 53: 10-Mbit/S Interface (Ports 00-23)

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 10-Mbit/s interface (ports 00–23) timing requirements (see Notes 3 through 6 and Figure 13) UNIT t c(THxCLK) † Cycle time, THxCLK T w(THxCLK) Pulse duration, THxCLK high or low t su(THxSYNC)

  • Page 54: 10-/100-Mbit/S Mac Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 THxCLK (input) THxSYNC (input) THxCOL THxCRS THxLINK THxRXD3–THxRXD0 THxRXDV (inputs) THxTXEN THxTXD3–THxTXD0 THxRENEG (outputs) Figure 13. 10-Mbit/s Interface (Ports 00–23) 10-/100-Mbit/s MAC interface Figures 14 and 15 show the timings at 100 Mbit/s and 10 Mbit/s for the 10-/100-Mbit/s port interfaces to the TNETE2101 devices.
  • Page 55 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 10-/100-Mbit/s transmit ports (24, 25, and 26) timing requirements (see Figure 15) UNIT t c(MxxTCLK) Cycle time, MxxTCLK t w(MxxTCLKL) Pulse duration, MxxTCLK low t w(MxxTCLKH) Pulse duration, MxxTCLK high...

  • Page 56: Sdram Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 SDRAM interface The SDRAM interface observes two types of timing: Multicycle timings between commands Subcycle timings between signals and DCLK Figure 16 illustrates the SDRAM interfaces signal timing in which each type of SDRAM command and its interrelated timings are shown.
  • Page 57 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 SDRAM subcycle operating characteristics over recommended operating conditions (see Figure 17) PARAMETER UNIT t c(DCLK) Cycle time, DCLK t w(DCLKL) Pulse duration, DCLK low t w(DCLKH) Pulse duration, DCLK high...

  • Page 58: Dio/Dma Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 DIO/DMA interface The DIO interface is asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces.
  • Page 59 TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 DIO/DMA read cycle timing requirements (see Figure 19) UNIT t w(SCSL) Pulse duration, SCS low t w(SCSH) Pulse duration, SCS high t su(SRNW) Setup time, SRNW high before SCS t su(SAD)

  • Page 60: Serial Mii Management Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 serial MII management interface timing requirements (see Figure 20) UNIT t su(MDIO) Setup time, MDIO valid before OSCIN , read t h(MDIO) Hold time, MDIO valid after OSCIN , read operating characteristics over recommended operating conditions (see Figure 20)

  • Page 61: Eeprom Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 EEPROM interface operating characteristics over recommended operating conditions (see Figure 21) TNETX3150 TNETX3150A PARAMETER PARAMETER UNIT UNIT f clock (ECLK) Clock frequency, ECLK t d (ECLKH–EDIOL) Delay time, from ECLK to EDIO (see Note 9)

  • Page 62: Led Interface

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 LED interface operating characteristics over recommended operating conditions (see Figure 22) PARAMETER UNIT t c(LEDCLK) Cycle time, LEDCLK t w(LEDCLKH) Pulse duration, LEDCLK high 48 †...

  • Page 63: Power-Up Oscin And Reset

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 power-up OSCIN and RESET timing requirements (see Figure 23) UNIT Frequency drift, OSCIN clock t c(OSCIN) Cycle time, OSCIN t w(OSCINL) Pulse duration, OSCIN low t w(OSCINH)

  • Page 64: Mechanical Data

    TNETX3270 ThunderSWITCH 24/3 ETHERNET SWITCH WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999 MECHANICAL DATA PGV (S-PQFP-G240) PLASTIC QUAD FLATPACK (DIE–DOWN) Heat Slug 0,27 0,08 0,17 0,50 0,16 NOM Gage Plane 29,50 TYP 0,25 32,20 0,25 MIN...
  • Page 65 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

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