Circuit Diagram - LG GM360i Service Manual

7. CIRCUIT DIAGRAM

12 11
L
K
J
PCB Rev. ADC table
PCB Ver. Resistance ADC value
Rev.A 3.9K(ERHZ0000278) 2292
Rev. B 8.2K(ERHZ0000319) 2557
I Rev.C 11.8K(ERHZ0000351) 2775
VBAT
BAT_ID W18
M_0
V17
Rev.D 16.9K(ERH0025401) 3080 RF_TEMP M_1
Y19
M_2
Y18
Rev. 1.0 24.9K(ERHY0000135) 3546 M_3
W17
M_4
AA18
M_5
PCB Ver. Y17
M_6
W16
M_7
AA17
M_8
VBAT. Mon. Y16
M_9
U15
M_10
K16
PA_LEVEL
PAOUT11
M12
PAOUT12
N15
I
BB_I
M15
H IX BB_IX
M16
Q BB_Q
QX K15
BB_QX
Shield in inner layer
TXON_PA E13
T_OUT0
B14
WLAN_WAKEUP T_OUT1
PA_BAND F11
T_OUT2
A15
WLAN_HOST_WAKEUP T_OUT3
BT_REG_ON E11
T_OUT4
F12
VIB_PWM T_OUT5
B13
PA_MODE
T_OUT6
_CHG_EOC C11
T_OUT7
E12
TOUCH_LDO_EN
T_OUT8
C12
LCD_BACKLIGHT_EN T_OUT9
B12
JACK_DETECT
T_OUT10
B15
_WLAN_RESET T_IN0
C13
_CHG_EN
T_IN1
G
D17
RF_EN RF_STR0
_PPR D18
RF_STR1
E15
RF_DA RF_DATA
RF_CLK B17
RF_CLK
C18
AFC
F_MODE W12
CLKOUT0
U12
26MHZ_MCLK
F26M VPLL_1V35(VDD_PLL)
H15
SWIF_TXRX
H16
SIM_IO CC_IO
F K18
SIM_CLK
CC_CLK
K17
SIM_RST CC_RST
E10
MMC_CMD MMCI1_CMD
A12
MMC_CLK
MMCI1_CLK
B11
MMC_DATA[0] MMCI1_DAT0
C9
MMC_DATA[1] MMCI1_DAT1
MMC_DATA[2] F10
MMCI1_DAT2
A14
MMC_DATA[3] MMCI1_DAT3
WLAN_CMD D3
MMCI2_CMD
D2
WLAN_D[0] MMCI2_DAT0
WLAN_CLK F6
MMCI2_CLK
_WP W11
FWP SD_1V8(VDDP_MEM)
TP103
F2
USB_OEN IRDA_TX
G2
BT_HOST_WAKEUP
VIO_2V62 IRDA_RX
E
A18
TDO
B18
TDI
C15
TMS
C16
TCK
F13
TRST_N
F16
RTCK
E14
TRIG_IN
B16
* Boot Mode MON1
C10
MON2
AA7
TRIG_IN TRACESYNC
U11
TRACECLK
Large Block P/U 1K Y9
PIPESTAT2
T10
Small Block P/D 10K PIPESTAT1
Y8
PIPESTAT0
D
TRACE32(14 Pin)
PIN NET PIN NET
1 2V8 2 GND
3 JTAGEN 4 GND
5 TDI 6 GND
7 TMS 8 GND
9 TCK 10 GND
C
11 TDO(DBB out) 12 _RESET
13 2V8 14 GND
TRACE32(20 Pin)
PIN NET PIN NET
1 2V8 2
3 JTAGEN 4 GND
5 TDI 6 GND
7 TMS 8 GND
B I2C1 I2C2
9 TCK 10 GND
11 I2C_SCL I2C_SDA I2C2_SCL I2C2_SDA
12 GND
PMIC CAMERA
13 TDO(DBB Out) 14 GND
TOUCH AUDIO AMP
15 _RESET 16 GND
MUIC
17 18 GND
CAMERA FLASH
19 20 GND
A
12 11
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
10 9 8
BASE BAND PROCESSOR
Star routing VMME_2V9 RTC_2V11 VAUDB_2V5
CORE_1V35 SD_1V8 SD_1V8 VIO_2V62 VSIM_2V9 VPLL_1V35
C130 C129
0.1u 0.1u
VAUDB_2V5(VDDA_M)
VAUDB_2V5(VDDA_BB)
VIO_2V62(VDDP_DIGC1)
U100
INST
SD_1V8(VDDP_DIGC2)
SD_1V8(VDDP_MEM)
VSIM_2V9(VDDP_SIM)
VMME_2V9(VDDP_MMC)
VIO_2V62(VDDP_DIGE)
VIO_2V62(VDDP_DIGE)
SD_1V8(VDDP_DIGC2)
VIO_2V62(VDDP_DIGC1)
VAUDB_2V5(VDDA_BG)
SD_1V8(VDDP_MEM)
VIO_2V62(VDDP_DIGC1)
VAUDA_2V5(VDDA_VBT)
VIO_2V62(VDDP_DIGD) VIO_2V62(VDDP_DIGB) VIO_2V62(VDDP_DIGE) VIO_2V62(VDDP_DIGA)
VAUDA_2V5(VDDA_VBR)
C127
0.1u
RCV_N
RCV_P
MMC_COVER_DET
Differential signal(shield)
C102 C101
39p 39p
Differential signal(shield)
10 9 8
7 6 5
VAUDA_2V5
ADD[16:29]
ADD[0:26]
ADD[0]
U8
MEM_A0
W4 ADD[1]
MEM_A1
SD_1V8(VDDP_MEM) ADD[2]
T8 ADD[0:15]
MEM_A2
U6 ADD[3]
MEM_A3
ADD[4]
W5
MEM_A4
AA4 ADD[5]
MEM_A5
ADD[6]
T7
MEM_A6
U7 ADD[7]
MEM_A7
ADD[8]
Y5
MEM_A8
AA5 ADD[9]
MEM_A9
W6 ADD[10]
MEM_A10
T9 ADD[11]
MEM_A11
W7 ADD[12]
MEM_A12
Y6 ADD[13]
MEM_A13
U9 ADD[14]
MEM_A14
W9 ADD[15]
MEM_A15
V1 ADD[16]
MEM_A16 ADD[17]
N5
MEM_A17
U2 ADD[18]
MEM_A18 ADD[19]
W2
MEM_A19
R5 ADD[20]
MEM_A20
ADD[21]
T1
MEM_A21
R4 ADD[22]
MEM_A22
ADD[23]
T2
MEM_A23
P5 ADD[24]
MEM_A24
ADD[25]
T3
MEM_A25
T4 ADD[26]
MEM_A26
M2 DATA[0] DATA[0:15]
MEM_AD0
L3 DATA[1]
MEM_AD1
J3 DATA[2]
MEM_AD2
L5 DATA[3]
MEM_AD3
M3 DATA[4]
MEM_AD4
N1 DATA[5]
MEM_AD5
P2 DATA[6]
MEM_AD6
N2 DATA[7]
MEM_AD7
J4 DATA[8]
MEM_AD8
K4 DATA[9]
SD_1V8(VDDP_MEM) MEM_AD9 DATA[10]
K5
MEM_AD10
L4 DATA[11]
MEM_AD11
DATA[12]
R1
MEM_AD12
M5 DATA[13]
MEM_AD13
DATA[14]
M4
MEM_AD14
P4 DATA[15]
MEM_AD15
R2
MEM_CS0_N _NAND_CS
P3 _RAM_CS
MEM_CS1_N
N3
MEM_CS2_N TP101
N4
MEM_CS3_N
U3 ADD[27]
MEM_CSA0_N
U4
ADD[28]
MEM_CSA1_N
T6
MEM_CSA2_N ADD[29]
T5
BA0
MEM_CSA3_N
T11
FCDP
FCDP_RBN
K2
MEM_WAITN
M1 BA1
MEM_ADVN
L1
_RD
MEM_RDN
R3
MEM_WRN _WR
W3
MEM_BFCLKO1
Y3
MEM_BFCLKO2 SDCLKI
Y2 SDCLKO
MEM_SDCLKO
AA2
MEM_BC0_N _BC0
V3 _BC1
MEM_BC1_N
U5
MEM_BC2_N LDQS
Y4 UDQS
MEM_BC3_N
Y7
_RAS
MEM_RAS_N
W8
MEM_CAS_N _CAS
U10
CKE
MEM_CKE
AA16 X100
F32K
AA15 2 1 FC-135
RTC_2V11(VDD_RTC) OSC32K
W14
_RESET 32.768KHz
RESET_N
VIO_2V62(VDDP_DIGA) H18 C105 C123
RSTOUT_N
Y14
RTC_2V11(VDD_RTC) RTC_OUT 22p 22p
RTC_OUT C131
R16
VREFP 220n VREFN
VAUDB_2V5(VDDA_BG) R15
IREF
RTC_2V11(VDD_RTC)
VDDP_DIGE J18
SPCU_RQ_IN0
J19
VDDP_DIGA SPCU_RQ_IN1
H17
SPCU_RC_OUT0
G18
SPCU_RQ_IN2
VIO_2V62
VIO_2V62 VIO_2V62
OJ207
7 6 5
- 115 -
4 3 2
Large Block Memory
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
ADD[16] TP114
D4
TP115
ADD[17] A0 DATA[0]
E4 P10 DATA[0:15]
ADD[18] A1 I_O0 DATA[1]
F4 N10
ADD[19] A2 I_O1 DATA[2]
G4 M10
ADD[20] A3 I_O2 DATA[3]
G8 L10
ADD[21] A4 I_O3 DATA[4]
F8 F10
ADD[22] A5 I_O4 DATA[5]
E8 E10
A6 I_O5
ADD[23] DATA[6]
D8 D10
ADD[24] A7 I_O6 DATA[7]
D9 C10
A8 I_O7
ADD[25] DATA[8]
G7 N11
ADD[26] A9 I_O8 DATA[9]
G5 M11
A10 I_O9
ADD[27] DATA[10]
F7 L11
ADD[28] A11 I_O10 DATA[11]
E7 K11
A12 I_O11
ADD[29] DATA[12]
E9 G11
ADD[0] A13 I_O12 DATA[13]
L4 F11
DQ0 I_O13
ADD[1] DATA[14]
M4 E11
ADD[2] DQ1 I_O14 DATA[15]
N4 D11
DQ2 U101 I_O15
ADD[3] L5
ADD[4] DQ3
M5 G3 TP107
ADD[5] DQ4 _CE _NAND_CS
N5 M3 TP108
_WR
ADD[6] DQ5 _WEN
M6 F3 TP109
ADD[7] DQ6 _RE _RD
N6 L3
ADD[16]
ADD[8] DQ7 ALE
M7 K3
ADD[9] DQ8 CLE ADD[17]
N7 E3
ADD[10] DQ9 R__B
L8 N3
ADD[11] DQ10 _WP SD_1V8
M8
ADD[12] DQ11
N8 H2
ADD[13] DQ12 VCCN1
L9
DQ13
ADD[14]
M9 C5
ADD[15] DQ14 VSS1 C137
N9 C9
DQ15 VSS2
0.1u
_BC0 K6 G2
LDQM VSS3
K7 H10
_BC1 UDQM VSS4
LDQS L6 P7
LDQS VSS5 SD_1V8
L7 P9
UDQS UDQS VSS6
SDCLKI C6
_CLK Caution!!! Need to GND shield in inner layer
C7 P5
SDCLKO CLK VSSQ
CKE D7
CKE
TP105 E5 C4
BA0 BA0 VDD1
TP110 F5 C8
BA1
BA1 VDD2
F6 P6
_RAS _RAS VDD3
E6
_CAS
_CAS
D6 P4
_WR _WED VDDQ1
TP106 D5 P8
_RAM_CS
_CS VDDQ2
C143 C138 C139 C141 C142
0.1u 0.1u 0.1u 0.1u 0.1u
Star routing
J-TAG
VBAT V_BUS
UART100
3G 2.5G
1
GND GND
2
UART_RX
RX RX
3
TX TX UART_TX
4
VCHAR NC1 R26
5 F_MODE
ON_SW ON_SW
6 10K
VBAT VBAT
7
PWR NC2
8
URXD NC3
9
UTXD NC4
10
DSR
11
RTS
12
CTS
OJ206
4 3 2
1
L
K
J
SD_1V8
I
FCDP
_WP
H
G
F
E
D
C
B
A
1
LGE Internal Use Only