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FMC
Connector
BS_CLK_SEL
BS_CLKI
S1
OSC
S2
20MHZ
ADG719
IN_CLK_SEL0
D0
2
2
0
CN_CKIP/N
1
0
CN_CKI
1
D1
IN_CLK_SEL1
NB6L72
AD_INCLK_OUT
Table 5-4 AD9518-3 PLL Reference source selection (PLL is enabled)
Setting
BS_CLK_SEL IN_CLK_SEL0
x
H
x
L
H
x
L
x
Table 5-5 Sampling Clock Distribution
Clock Source
AD9518-3
0x1E1[1:0]
Internal VCO
[1,0]
(f
)
VCO
CLK input (f
)
[0,0]
CLK
IN_CLK_SEL1
0
CN_CKIP/N
[0,1]
1
CN_CKI
RFM-DACNF01-P500MH
0
REF1
0
1
REF2
1
REG
0x01C[6]
LF
VCO
1
0
Q0
REG
0x1E1[1]
CLK+
Q1
CLK-
REG
0x1E1[0]
AD9518
Figure 5-3 The Block Diagram of Clock Distribution
Remarks
AD9518-3 Register
PLL REF source
0x01C[6,2,1]
[0,0,1]
TCXO (20MHz)
[0,0,1]
BS CLKI (from FMC Carrier)
[1,1,0]
CN_CKI (Single ended) on Front Panel
[1,1,0]
CN_CKIP/N (Differential) on FMC
Register Setting
VCO Divider
CH Divider
2 to 6
1
2 to 32
2 to 6
1
(f > 1600MHz)
2 to 32
Bypass
1
(f < 1600MHz)
2 to 32
- 5 -
Hardware Reference Manual
Filter
÷R
PFD
CP
÷N
REG
0x1E0[2:0]
÷(2 to 6)
1
0
REG
1
0x191[7]
1
0
0
÷(2 to 32)
REG
0x192[1]
REG
1
0x194[7]
1
0
0
÷(2 to 32)
REG
0x195[1]
REG
1
0x197[7]
1
0
÷(2 to 32)
0
REG
0x198[1]
AD Clock
Direct Out
1
f
VCO
0
f
VCO
1
f
CLK
0
f
CLK
0
f
CLK
0
f
CLK
ver.10
CP
FMC
Connector
OUT0
AD_SYSCLKP/N
2
2
OUT1
OUT2
OUT3
OUT4
OUT5
Input
REF1
REF1
REF2
REF2
÷ (2 to 6)
÷{ (2 to 6)×(2 to 32) }
÷ (2 to 6)
÷{ (2 to 6)×(2 to 32) }
÷ 1
÷ (2 to 32)
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