Reference Documents - K.K. Rocky RFM-DACNF01-P500MH Hardware Reference Manual

Table 5-6 The Signal Assignment to FMC Connector (continued)
Signal
Pin# FMC_LOC
F 1 AD_PGOOD PG_M2C
E 2 BS_CLKp HA01_P_CC
E 3 BS_CLKn HA01_N_CC
G 18 IN_CLK_SEL0 HA16_P
K 19 PLL_nCS HA21_P
K 20 PLL_nRST HA21_N
J 21 PLL_MON HA22_P
J 22 PLL_SDIO HA22_N
K 22 PLL_LOCK HA23_P
K 23 PLL_SCLK HA23_N
H 4 SYSCLKp CLK0_M2C_P O
H 5 SYSCLKn CLK0_M2C_N O
G 33 BS_CLK LA31_P
G 34 BS_CLK_SEL LA31_N
G 37 IN_CLK_SEL1 LA33_N
G 36 INCLK_OUT LA33_P

6. Reference Documents

(1) FPGA Mezzanine Card (FMC) Standard
(2) MAX5888 Data Sheet （MAXIM)
(3) AD9518-3 Data Sheet （Analog Devices)
RFM-DACNF01-P500MH
I/O Function
O Power Good
O Selected External clock
O Selected External clock
I CN_CKIP/ CN_CKIN Select
I PLL (AD9518) Chip Select
I PLL (AD9518) Reset
O PLL (AD9518) Reference monitor
I/O PLL (AD9518) Serial Control Port data I/O
O PLL (AD9518) Lock detect
I PLL (AD9518) Serial Control port Clock
PLL (AD9518) LVPECL Output
PLL (AD9518) LVPECL Output
I PLL Reference Clock from FMC Carrier
I Reference Clock Select
I Input Clock Select
O Clock Input Monitor
ANSI/VITA 57.1
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Hardware Reference Manual
Remarks
Refer to Table 5-4
Refer to Table 5-5
ver.10