RFM-DACNF01-P500MH Hardware Reference Manual ver.10 Revision History Issue Date Changes Made ver1.0 2017/05/23 First Release Table of Contents 1) Preface 2) Safety Instructions 1. Introduction ……………………………………………………………………………………… 2. Main Components ………………………………………………………………………………… 3. Block Diagram …………………………………………………………………………………… 4. Board Layout …………………………………………………………………………………… 5. Board Specifications ………………………………………………………………………………...
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1) Preface Thank you for choosing RFM-DACNF01-P500MH FMC board. This manual describes the features and specifications of the RFM-DACNF01-P500MH FMC board. Read and understand the contents of this manual before operating this board. K.K.Rocky reserves the right to revise this document and to make changes without notice.
1. Introduction The RFM-DACNF01-P500MH is an ANSI/VITA57-1 compliant FPGA Mezzanine Card (FMC) which offers one 16bits DA channel up to 500MSPS. It works on a High Pin Count (HPC) site of FMC carrier board from K.K.Rocky or third party.
RFM-DACNF01-P500MH Hardware Reference Manual ver.10 5.2 Power Table 5-2 shows the required power of the board. All Powers are supplied from FMC carrier board through FMC connector. Table 5-2 Power Item Voltage Current Remarks 12P0V +12V 300mA (Max) 3P3V +3.3V...
MAX5988 DA0~DA1 x=0~1 Figure 5-2 Signal Flow Block diagram DA1 portion is mounted as default for RFM-DACNF01-P500MH. However DA0 can be mounted as factory option instead of DA1. PLL Clock Distribution Figure 5-3 shows the block diagram of PLL clock distribution.
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RFM-DACNF01-P500MH Hardware Reference Manual ver.10 Table 5-6 shows the signal assignment to FMC connector. Table 5-6 The Signal Assignment to FMC Connector Pin# Signal FMC_LOC I/O Function Remarks C 30 SCL I2C Clock C 31 SDA I/O I2C Data C 34 GA0...