Table of Contents
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1. Introduction
The RFM-DACNF01-P500MH is an ANSI/VITA57-1 compliant FPGA Mezzanine Card (FMC) which offers one
16bits DA channel up to 500MSPS.
It works on a High Pin Count (HPC) site of FMC carrier board from K.K.Rocky or third party.
2. Main Components
The main components of the board are listed on Table 2-1.
Table 2-1 Main Components
Item
FMC Connector (HPC)
DA Converter
PLL Clock Generator
EEPROM (I2C)
External Clock Input Connector
External Clock Input Connector
(Reference) Mating Cable
3. Block Diagram
Figure 3-1 shows the block diagram of the board.
TCXO
20MHz
CN_CKIP/N
2
CN_CKI
CN_DA1_P
IOUTP
IOUTN
CN_DA1_N
Not mounted
CN_DA0_P
IOUTP
IOUTN
CN_DA0_N
RFM-DACNF01-P500MH
Description
ASP-134488-01 (SAMTEC)
MAX5888AEGK+D (MAXIM)
D9518-3
BR24L01AFV-WE2 (Rohm)
MMCX-LR-PC-1 (40) (Hirose)
MMCX-R-PC (40) (Hirose)
RF316-01SP1-03SP1-0500 (SAMTEC)
1
AD9518(PLL)
S
REF+
W
2
1
2
0
D0
S
REF-
W
2
1 2
D1
CLK
SPI
MAX5888
MAX9123
B0P/N
2 X 16
:
B15P/N
PD
SEL0
CLKP/N
MAX9123
MAX5888
CLKP/N
MAX9123
2 X 16
B0P/N
:
B15P/N
PD
SEL0
Figure 3-1 Block Diagram
Hardware Reference Manual
FMC(HPC)
2
2
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
4
VADJ=2,5V
16
X4
VADJ=2,5V
VADJ=2,5V
16
X4
EEPROM
- 1 -
ver.10
Remarks
on Front Panel
on Board
This is not shipped with Board
IN_CLK_SEL1
LPC
BS_CLK
BS_CLK_SEL
AD_INCLK_OUT
AD_SYSCLK
HPC
PLL_SPI
IN_CLK_SEL0
DA1_D0
:
DA1_D15
DA1_PD
DA1_SEL0
DA1_CLK
DA0_CLK
LPC
DA0_D0
:
DA0_D15
DA0_PD
DA0_SEL0
SCL
SDA
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