Signal Flow; Pll Clock Distribution - K.K. Rocky RFM-DACNF01-P500MH Hardware Reference Manual

5.4 Signal Flow

Figure 5-2 shows the block diagram of signal flow.
S1
OSC
S2
20MHz
ADG719
2
D0
CN_CKIP/N
CN_CKI D1
NB6L72
SEL1 Q1
L
H
CN-DAx-P
CN-DAx-N
DA0～DA1 x=0～1
DA1 portion is mounted as default for RFM-DACNF01-P500MH.
However DA0 can be mounted as factory option instead of DA1.
5.5

PLL Clock Distribution

Figure 5-3 shows the block diagram of PLL clock distribution.
AD9518-3 clock distribution is described on Table 5-4 and Table 5-5.
Refer to AD9518-3 data sheet for further details of device operation.
RFM-DACNF01-P500MH
IN D
L S1
IN
H S2
D Ref+
Ref-
2
Q1 CLK
MC100EPT21
AD9518
Q0
SEL1
SEL0
SEL0 Q0
D0 L D0
D1 H D1
CLK
D0
IOUTP
IOUTN D15
PD
SEL0
MAX5988
Figure 5-2 Signal Flow Block diagram
Hardware Reference Manual
2
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
Reg:0x01C
CS
SCLK
SDIO
REFMON
LD
RESET
2
2
2
MAX9123 X5
- 4 -
ver.10
BS_CLK1 (LA31_P)
BS_CLK_SEL(LA31_N)
AD_SYSCLKp/n
(CLK0_M2C_P/N)
PLL_nCS (HA21_P)
PLL_SCLK (HA23_N)
PLL_SDIO (HA22_N)
PLL_MON (HA22_P)
PLL_LOCK (HA23_P)
PLL_nRST (HA21_N)
AD_INCLK_OUT(LA33_P)
IN_CLK_SEL1(LA33_N)
IN_CLK_SEL0(HA16_P)
DAx_D0
DAx_D15
DAx_PD
DAx_SEL0
HPC