Block Diagram - JVC RX-8012PSL Service Manual

RX-8012PSL
Description of major ICs
AK4112A (IC551) : 96kHz 24bit DIR
1. Pin layout
DVDD 1
DVSS 2
TVDD 3
V/TX 4
XTI 5
XTO 6
PDN 7
Top
View
R 8
AVDD 9
AVSS 10
RX1 11
RX2/DEF0 12
RX3/DEF1 13
RX4/DEF2 14
3. Pin function
No. Pin Name I/O
1 DVDD - Digital Power Supply Pin, 3.3V
2 DVSS -
Digital Ground Pin
3 TVDD - Input Buffer Power Supply Pin, 3.3V or 5V
4 V O Validity Flag Output Pin in parallel mode
TX O Transmit channel (through data)
Output Pin in serial mode
5 XTI I X'tal Input Pin
6 XTO O
X'tal Output Pin
7 PDN I Power-down mode Pin
When "L", the AK4112A is powerd-down and reset.
8 R - External resister pin
18Kohm +/-1% resistor to AVSS externally.
9 AVDD - Analog Power Supply Pin
10 -
AVSS Analog Ground pin
11 RX1 I Receiver Channel 1
This channel is selected in parallel mode
or default of serial mode.
12 DIF0 I Audio Data Interface format 0 Pin in parallel mode
RX2 I Receiver Channel 2 in serial mode
I
13 DIF1 Audio Data Interface format 1 Pin in parallel mode
RX3 I Receiver Channel 3 in serial mode
14 DIF2 I Audio Data Interface format 2 Pin in parallel mode
RX4 I Receiver Channel 4 in serial mode
15 AUTO O Non-PCM Detect Pin
"L": No detect, "H": Detect
1-12
28 CM0/CDTO
27 CM1/CDTI
26 OCKS1/CCLK
25 OCKS0/CSN
24 MCKO1
23 MCKO2
22 DAUX
V/TX
21 BICK
20 SDTO
DVDD
19 LRCK
DVSS
18 ERF
17 FS96
16 P/SN
15 AUTO
Function

2. Block diagram

AVSS AVDD
RX1 Clock
Recovery
RX2
Input
Selector
RX3
RX4
DAIF
Decoder
System
Control
AC-3/MPEG
Detect
PDN
AUTO
No. Pin Name I/O
16 P/S I
17 FS96 O
18 ERF O
19 LRCK I/O
20 SDTO O
21 BICK I/O
22 DAUX I
23 MCKO2 O
24 MCKO1
O
25 OCKS0 I
CSN I
26 OCKS1 I
CCLK I
27 CM1
I
CDTI I
28 CM0 I
CDTO O
Note: All input pins except internal pull-down pins should not be left floating.
R MCKO1 MCKO2 XTI XTO
Clock X'tal
Generator Oscillator
96kHz
Detect
DEM
Audio
uP I/F
Error
Detect
ERF P/S="L"
Function
Parallel / Serial Select Pin
"L": Serial mode, "H": Parallel mode
96kHz sampling detect pin
(RX mode) "H" : fs=88.2kHz or more,
"L" fs=54kHz or Iess.
(X'tal mode) "L" : XFS96=1, "L" : XFS96=0.
Unlock & Parity Error Output Pin
"L": No error, "H": Error
Output Channel Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Auxiliary audio data input pin
Master Clock #2 Output Pin
Master Clock #1 Output Pin
Output Clock Select 0 Pin in parallel mode
Chip Select Pin in serial mode
Output Clock Select 1 Pin in parallel mode
Control Data Clock Pin in serial mode
Master Clock Operation Mode Pin in parallel mode
Control Date Input Pin in serial mode
Master Clock Source select Pin in parallel mode
Control Date Output Pin in serial mode
FS96
DAUX
LRCK
BICK
SDTO
I/F
TVDD
CSN
CCLK
CDTO
CDTI