Motorola XTS 2500 Service Manual page 129

700/800 MHz Detailed Theories of Operation: VOCON Functional Blocks
One-Wire Interface
The MCU has a One-Wire Interface module that is used to communicate to a One-Wire device like a
USB cable or a smart battery using the Dallas Semiconductor protocol. This module has one
external pin, OWIRE_DAT (U800 pin F6), and it uses the GPIO voltage logic level.
4.4.6.1.1.2 Digital Signal Processor (DSP)
The DSP portion of the Patriot has 84Kx24 bits of program RAM and 62Kx16 bits of data RAM.The
DSP has its own set of peripherals including the following:
• the Baseband Interface Port (BBP)
• the DSP Timer module, and
• the Serial Audio Codec Port (SAP).
Additionally, the DSP shares some peripherals with the MCU, including the USB interface and the
General Purpose Input/Output module (GPIO).
Baseband Interface Port (BBP)
The Baseband Interface Port (BBP) module is the DSP's serial synchronous interface (SSI) to the
RF board. The BBP has independent sections for the receiver and the transmitter. The receiver BBP
pins include
• the receive data pin SRDB
• the receive clock signal pin SC0B, and
• the receive frame synchronization (sync) signal pin SC1B.
The transmitter's BBP pins include
• the transmit data pin STDB (R816)
• the transmit clock signal pin SCKB (TCLK test point), and
• the transmit frame sync signal pin SC2B (TSYNC).
All BBP lines use the GPIO voltage level (see section 4.4.6.1.1.).
DSP Timer Module
While the BBP receive clock and frame sync signals are supplied by the ABACUS III from the RF
board, the BBP transmit clock and frame sync signals are generated by the MAKO IC using the
16.8MHz clock (connected to the TCXO_IN M1 pin). The BBP transmit clock and frame sync signals,
along with the BBP transmit data signal, are connected to the Digital-to-Analog Converter (DAC) on
the RF board.
Serial Audio Codec Port (SAP)
The Serial Audio Codec Port (SAP) module is the DSP's serial synchronous interface (SSI) to the
audio codec on the MAKO IC. The SAP interface consist of four signals:
• the SAP clock line pin SCKA (CODEC_DCLK, R772)
• the SAP frame sync line pin SC2A (CODEC_FSYNC, R773)
• the SAP receive data line pin SRDA (CODEC_TX, R774), and
• the transmit data line pin STDA (CODEC_RX, R775).
The SAP clock is generated by the MAKO IC, U701, and it is a 512kHz, 2.9-volt peak-to-peak wave.
The SAP frame sync signal is also generated by the MAKO IC, U701 and it is an 8 kHz, 2.9-volt
peak-to-peak square wave.
6816985H01-F
4.4-7
February 14, 2012