Panasonic KX-FP81BX Service Manual page 133

6.3.7. RESET CIRCUIT (WATCH DOG TIMER)
The output signal from pin 1 of the voltage detect IC (IC509) is input to the ASIC (IC501) 112 pin. Then the output signal from pin
109 of the ASIC (IC501) resets the ASIC.
1. During a momentary power interruption, a positive reset pulse of 46~51 msec is generated and the system is reset completely.
2. When pin 108 and 109 of IC501 become low level, they will prohibit the SRAM (IC504) from changing data.
The SRAM (IC504) will go into the backup mode, when they are backed up by a lithium battery.
3. The watch dog timer, built-in the ASIC (IC501), is initialized by the CPU about every 1.5 ms.
When a watch dog error occurs, pin 113 of the ASIC (IC501) becomes low level.
The terminal of the ´WDERR´ signal is connected to the reset line, so the ´WDERR´ signal works as the reset signal.
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KX-FP81BX / KX-FP81CX / KX-FP82CX