Motorola ASTRO XTS 5000 Detailed Service Manual page 61

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3.2.2.2 Static RAM (SRAM) U403
The static RAM (SRAM) IC U403 is an asynchronous, 1 MB, CMOS device that is capable of 70 ns
access speed. It is supplied with 1.8 volts. The SRAM has its 19 address lines and 16 data lines
connected to the EIM of the Patriot IC through the Address(23:0) and Data(15:0) busses.
The SRAM has an active-high chip select CS2 that is tied directly to the 1.8 V supply and an active-
low chip select CS1 that is connected to the EIM CS2_N pin (test point CS2). When the SRAM CS1
pin is not asserted, the SRAM is in standby mode, which reduces current consumption.
Two other control signals from the EIM that change the mode of the SRAM are the read/write signal,
R/W, and the output enable signal, OE. The R/W of the EIM is connected to the SRAM EN_WE pin
(test point R_W), while the OE signal from the EIM is connected to the SRAM EN_OE pin. The
SRAM is in read mode when the EN_WE pin is not asserted and the EN_OE pin is asserted. The
SRAM is in write mode when the EN_WE pin is asserted, regardless of the state of the EN_OE pin.
The other SRAM pins are the lower-byte enable pin LB and the upper-byte enable pin UB. These
pins are used to determine which byte (LB controls data lines 0-7 and UB controls data lines 8-15) is
being used when there is a read or a write request from the Patriot IC. The LB pin is controlled by the
EIM EB1_N signal, while the UP pin is controlled by the EB0_N signal.
3.2.2.3 FLASH Memory U402
The Flash memory IC is an 8 MB CMOS device with simultaneous read/write or simultaneous read/
erase operation capabilities with 70 ns access speed. It is supplied with 1.8 volts. The Flash memory
has its 22 address lines and 16 data lines connected to the EIM of the Patriot IC through the
Address(23:0) and Data(15:0) busses. The Flash memory contains host firmware, DSP firmware,
and codeplug data with the exception of the tuning values that reside on the transceiver board's
serial EEPROM. The Flash memory IC is not field repairable.
The RESET_OUT of the Patriot IC is at a GPIO voltage logic level. Components D401 and R401 are
used to convert the voltage down to a 1.8 V logic level, and this 1.8 V reset signal is fed to the Flash
RESET pin. When this pin is asserted (active low logic), the Flash is in reset mode. In this mode, the
internal circuitry powers down, and the outputs become high-impedance connections.
The Flash active-low chip select pin, EN_CE, is connected to the active-low CS0_N pin (CS0 test
point) of the EIM. When the EN_CE is not asserted, the Flash is in standby mode, which reduces
current consumption.
Several other active-low control pins determine what mode the Flash memory is in: the address valid
pin ADV (ADV test point) that is connected to the EIM LBA_N signal, the output enable pin EN_OE
that is connected to the EIM OE_N signal, and the write enable pin EN_WE that is connected to the
EIM EB1_N signal. For read mode, the ADV and EN_OE pins are asserted while the EN_WE pin is
not asserted. When the EN_WE is asserted and the EN_OE pin is unasserted, the Flash operates in
the write mode.
Figure 3-9 illustrates the EIM and memory ICs block diagram.
November 16, 2006
Theory of Operation
: VOCON Board
6881094C31-E