Casio UP-250 Technical Manual page 53

CPU pin functions
Pin CPU
Signal Name
No. Function
24 X1 X1
25 X2 X2
26 EA EA
27 P75 P75 (A16)
28 P76 P76 (A17)
29 P77 P77 (A18)
30 P80 WDTOUT
31 P81/INT0 CLK IN/DTR
32 P82 PF SW
33 ALE ALE
34 VCC VCC
35 AD AD0
36 AD AD1
37 AD2 AD2
38 AD3 AD3
39 AD4 AD4
40 AD5 AD5
41 AD6 AD6
42 AD7 AD7
43 A8 A8
44 A9 A9
45 A10 A10
46 A11 A11
47 A12 A12
48 A13 A13
49 A14 A14
50 A15 A15
51 VSS VSS
52 P20 CR A/DSW1
53 P21 CR B/DSW2
54 P22 CR C/DSW3
55 P23 CR D/DSW4
I/O Level Description
Connected to ceramic vibration generator.
I ---
f=14.74 MHz ± 0.5%.
O --- Connected to ceramic. f=14.74 MHz ± 0.5%.
External memory access. LOW: external ROM
I TTL
HIGH: internal ROM (CPU mask).
O TTL External memory address A16 (software).
O TTL External memory address A17 (software).
O TTL External memory address A18 (software).
Watch dog timer error (and hardware limited
O TTL
time power supply switch). LOW: error (reset).
I TTL Connected to pin #19.
I TTL Paper feed switch. LOW: active.
Address latch enable signal. Latches address
O TTL
on bus AD0 to AD7 at fall.
I (+5 V) Main power terminal (+5 V).
Address/data bus.
3-state TTL
Transmits address (lower 8 bits) and data.
O TT LAddress bus (address upper 8 bits).
I (0 V) GND terminal.
Carriage motor driver control 2-2 phase
excitation. All terminals on (LOW): hold.
I/O TTL
DIP SW 1-1 to 1-4 read when P100, P101 are
LOW.
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