Sony PEGA-CC5 Service Manual page 50

PEGA-CC5
• MAIN BOARD IC14 TC200G58EFG-0007 (ASIC)
Pin No. Pin Name
1 T2
2 VDD
3 VSS
4 FM_ON
5 FMCE
6 FMCLK
7 FMDATA
8 FMMUTE
9 SPMUTE
10 CMUTE
11 SBUSMUTE
12 VSS
13 CLIE_POWER
14 CHARGE
15 HOTSYNC
16 UNREG_OUT
17 VSS
18 VDD
19 to 25 BA0 to BA6
26 VDD
27 VSS
28 to 33 BA7 to BA12
34 ALE
35 VSS
36 VDD
37 VSS
38 to 43 BD0 to BD5
44 VSS
45 to 50 BD6 to BD11
51 VSS
52 VDD
53, 54 BD12, BD13
55 VSS
56, 57 BD14, BD15
58 RD
59 WR
60 CS0
61 CS1
62 VSS
63 DCLK
64 VSS
65 VDD
66 to 70 INT0 to INT4
71 CLK32K
72 VSS
50
I/O
— Not used
— Power supply terminal (+3.3V)
— Ground terminal
O Power on/off control signal output for the FM transmitter
O Chip enable signal output to the FM transmitter
O Serial data transfer clock signal output to the FM transmitter
O Serial data output to the FM transmitter
O Muting on/off control signal output to the FM transmitter
O Muting on/off control signal output to the speaker amplifier
O Muting on/off control signal output for the line output
O Muting on/off control signal output for the SONY bus Not used
— Ground terminal
O Power control signal output for a CLIE Not used
O Charge on/off control signal output for a CLIE
O HOT-SYNC signal output to a CLIE
I Cradle detection input of a CLIE
— Ground terminal
— Power supply terminal (+3.3V)
I Address signal input from the CPU
— Power supply terminal (+3.3V)
— Ground terminal
I Address signal input from the CPU
I Address latch signal (upper byte) input from the CPU
— Ground terminal
— Power supply terminal (+3.3V)
— Ground terminal
I/O Two-way data bus with the CPU and flash memory
— Ground terminal
I/O Two-way data bus with the CPU and flash memory
— Ground terminal
— Power supply terminal (+3.3V)
I/O Two-way data bus with the CPU and flash memory
— Ground terminal
I/O Two-way data bus with the CPU and flash memory
I Data read enable signal input from the CPU
I Write strobe signal input from the CPU
I Chip select signal input from the CPU
I Chip select signal input from the CPU
— Ground terminal
I Clock signal input from the CPU
— Ground terminal
— Power supply terminal (+3.3V)
O Interrupt request signal output to the CPU
O Not used
— Ground terminal
Description