u-blox AMY-5M Hardware Manual page 20

slaves can respond but also enables and synchronizes designated slaves to physically access the bus by driving
the clock. Although multiple nodes can assume the role of a master, only one at any time is permitted to do so.
Thus, when one node acts as master, all other nodes act as slaves. Table 3 shows the possible roles and modes
for devices connected to a DDC bus.
Master: sends the clock and addresses slaves
Slave: receives the clock and address
Table 3: Possible roles and modes of devices connected to DDC bus
u-blox 5 GPS receivers normally run in the slave mode. There is an exception when an external EEPROM is
attached. In that case, the receiver attempts to establish presence of such a non-volatile memory component by
writing and reading from a specific location. If EEPROM is present (assumed to be located at a fixed address
0xA0), the receiver assumes the role of a master on the bus and never changes role to slave until the following
start-up (subject to EEPROM presence). This process takes place only once at the start-up, i.e. the receiver's role
cannot be changed during the normal operation afterward. This model is an exception and should not be
implemented if there are other participants on the bus contending for the bus control (µC / CPU, etc.).
As a slave on the bus, the u-blox 5 GPS receiver cannot initiate the data transfers. The master node has the
exclusive right and responsibility to generate the data clock, therefore the slave nodes need not be configured to
use the same baud rate. For the purpose of simplification, if not specified differently, SLAVE denotes the u-blox 5
GPS receiver while MASTER denotes the external device (CPU, μC) controlling the DDC bus by driving the SCL
line.
u-blox GPS receivers support standard mode I
transfer rate up to 100 kbit/s.
2.3.3.2 Communicating to a slave with the GPS receiver as master
Pins SDA2 and SCL2 have internal pull-ups. If capacitive bus load is large, additional external pull-ups may be
needed in order to achieve the desired data rates.
Table 4 lists the maximum total pull-up resistor values for the DDC interface. The pull-up resistors integrated in
the pads of the baseband-IC can simply be ignored for high capacitive loads. However, for small loads, e.g. if just
connecting to an external EEPROM, these built-in pull-ups are sufficient.
Load Capacitance Pull-Up Resistor Value R20, R21
50 pF
18 k
100 pF
9 k
250 pF 4 k
Table 4: Pull-up resistor values for DDC interface
2
Serial I C memory can be connected to the DDC interface. It will automatically be recognized by firmware. The
memory address must be set to 0b1010000 and the size fixed to 4 kB.
GPS.G5-MS5-08207-A3
Transmit
Sends data to slave
Sends data to master
2
C-bus specification with 7-bit addressing and a data
Preliminary
AMY-5M - Hardware Integration Manual
Receive
Receives data from slave
Receives data from master
Design-in
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