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For most DDC systems the low and high input voltage level thresholds of SDA and SCL depend on V
receiver datasheet for the applicable voltage levels.
DDC Device A
SDA in
SDA out
SCL in
SDA out
Figure 11: A simple DDC connection
The signal shape and the maximum rate in which data can be transferred over SDA and SCL is limited by the
values of Rp and the wire and I/O capacitance (Cp). Long wires and a large number of devices on the bus
increase Cp, therefore DDC connections should always be as short as possible. The resistance of the pull-up
resistors and the capacitance of the wires should be carefully chosen.
Rp
Figure 12: DDC block diagram
2.3.3.1
Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it's a microcontroller,
EEPROM or D/A Converter, etc) and can operate as either a transmitter or receiver, depending on the function of
the device. The default DDC address for u-blox GPS receivers is set to 0x42. Setting the mode field in the CFG-
PRT message for DDC accordingly can change this address.
The first byte sent is comprised of the address field and R/W bit. Hence the byte seen on the bus 0x42 is
shifted by 1 to the left plus R/W bit thus being 0x84 or 0x85 if analyzed by scope or protocol analyzer.
In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. At that time, any device addressed is considered a slave. The DDC-bus is a multi-master bus,
i.e. multiple devices are capable of controlling the bus. Such architecture is not permanent and depends on the
direction of data transfer at any given point in time. A master device not only allocates the time slots when
GPS.G5-MS5-08207-A3
V
DD
Rp
Rp
SDA
SCL
GND
Rp
AMY-5M - Hardware Integration Manual
DDC Device B
SDA in
SDA out
SCL in
SDA out
Preliminary
. See
DD
Design-in
Page 19 of 54
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