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u-blox UBX-G7020 Hardware Integration Manual

u-blox UBX-G7020 Hardware Integration Manual

7 gps/gnss chips
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UBX-G7020
u-blox 7 GPS/GNSS chips
Hardware Integration Manual
Highlights:
u-blox 7 position engine featuring excellent accuracy and
time-to-first-fix performance
Multi-GNSS engine for GPS, GLONASS, Galileo and QZSS
AssistNow Online, Offline and Autonomous for faster TTFF
Minimal board space
Low power consumption
Minimal e-BOM
www.u-blox.com
GPS.G7-HW-10003
UBX-G7020 - Hardware Integration Manual
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  • Page 1 UBX-G7020 - Hardware Integration Manual UBX-G7020 u-blox 7 GPS/GNSS chips Hardware Integration Manual Highlights: u-blox 7 position engine featuring excellent accuracy and time-to-first-fix performance Multi-GNSS engine for GPS, GLONASS, Galileo and QZSS AssistNow Online, Offline and Autonomous for faster TTFF Minimal board space...
  • Page 2 QFN40 package (Automotive grade) This document and the use of any information contained therein, is subject to the acceptance of the u-blox terms and conditions. They can be downloaded from www.u-blox.com. u-blox makes no warranties based on the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.

  • Page 3: Preface

    Application Note: This document provides general design instructions and information that applies to all u-blox GPS receivers. See section Related documents for a list of Application Notes related to your GPS receiver.
  • Page 4 Helpful information when contacting technical support When contacting Technical Support please have the following information ready: Chipset type (e.g. UBX-G7020-KT) and revision (e.g. A0100) Receiver configuration Schematic at least of the GPS section of your circuit Layout of the GPS section of your circuit and the PCB stack-up.

  • Page 5: Table Of Contents

    UBX-G7020 - Hardware Integration Manual Contents Preface ..........................3 Contents ..........................5 Hardware Description ....................8 Overview .............................. 8 Architecture ............................8 Design-in ........................9 Power management ........................... 10 2.1.1 Power domains..........................10 2.1.2 Supply voltages ........................... 12 2.1.3 Built in supply monitors ....................... 15 2.1.4...
  • Page 6 UBX-G7020 - Hardware Integration Manual 2.6.1 General notes on interference issues ................... 32 2.6.2 RF front-end circuit options ......................34 USB ..............................38 JTAG ..............................39 Layout ..............................40 2.9.1 Placement ........................... 40 2.9.2 Package footprint, copper and solder mask ................. 40 2.10...
  • Page 7 UBX-G7020 - Hardware Integration Manual Production ........................60 Packaging, shipping, storage and moisture preconditioning ............... 60 ESD handling precautions ........................60 Soldering ............................60 Production ............................61 5.4.1 Set the Low Level Configuration and program the optional SQI flash .......... 62 5.4.2...

  • Page 8: Hardware Description

    G7020 positioning chips the ideal solutions for cost sensitive applications that don’t require firmware update capability. For applications needing firmware update capability or taking advantage of the data logging feature the UBX-G7020 can be connected to an external SQI FLASH memory. Lower price GPS/GNSS crystals as well as high performance TCXOs are also supported.

  • Page 9: Design-In

    UBX-G7020 - Hardware Integration Manual 2 Design-in In order to obtain good performance with UBX-G7020 chip design, there are a number of points that require careful attention during the design-in. These include: Power Supply: Good performance requires a clean and stable power supply.

  • Page 10: Power Management

    VDD_IO to V_BCKP in case of power failure at VDD_IO. The control registers for the UBX-G7020 are located in the backup domain - an always on domain which means if the backup domain is not supplied, all the other domains will not be turned on. All the GPS/GNSS orbit data and time are maintained in the backup memory to which the functional configuration can also be saved.
  • Page 11 UBX-G7020 - Hardware Integration Manual 2.1.1.2 Core domain The voltage for the core domain is generated by LDO_C and is supplied by V_CORE. The core domain is the main digital power domain and consists of the largest blocks in the chip and sinks most of the current. When it is switched off, the RF power domain is also switched off.

  • Page 12: Supply Voltages

    To improve the power consumption, the supply for V_CORE can be generated with the optional built in DCDC converter. It generates an output voltage of ~1.45V. Figure 3: UBX-G7020’ PMU using DCDC converter The DC/DC block provides an energy conversion efficiency of about 85%, the actual value depending on current drawn and external inductor L2 and capacitor C6 used.
  • Page 13 UBX-G7020 - Hardware Integration Manual Figure 4: Power Savings using DCDC converter For a 1.8V supply it does not make sense to use the DC/DC converter; the power savings are marginal (~5%). By default the DC/DC converter is disabled. The DC/DC converter has to be enabled by the Low Level Configuration. See section 2.10.2.
  • Page 14 2.1.2.4 VDD_ANA and VDD_LNA VDD_ANA is the supply for all the analogue parts in the UBX-G7020. VDD_LNA is the supply for the low noise amplifier inside the UBX-G7020. VDD_ANA and VDD_LNA must be supplied by VDD_RF_OUT. If a clean power supply cannot be provided at V_CORE (which supplies the LDO_RF), it is recommended to add external filtering (FB1 and C3) to supply VDD_ANA/ VDD_LNA.

  • Page 15: Built In Supply Monitors

    2.1.4.2 Power Save Mode u-blox 7 GPS/ GNSS receivers include two Power Save Mode operations called ON/OFF and Cyclic tracking that allow reducing the average current consumption in different ways to match the needs of the specific application. Both operations can be set and configured by sending the corresponding UBX messages to the receiver. For more information, please see the u-blox 7 Receiver Description including Protocol Specification [3] In Power Save Mode, the supply voltages (V_CORE and VDD_IO) must remain inside operating conditions.

  • Page 16: Pios

    2.2 PIOs There are 17 PIOs, PIO0 to PIO16, available on the UBX-G7020. All the PIOs are supplied by VDD_IO, thus all the voltage levels of the PIO pins are related to VDD_IO supply voltage. All the inputs have internal pull-up resistors in normal operation.

  • Page 17: Sqi Flash Memory

    Low Level Configuration, see section 2.10.2! Place the SQI FLASH close to the UBX-G7020 chip to keep the interface lines short and if possible route them on inner layers to avoid noise emission. Also make sure that all the lines are not too-long/ too-thick to reduce capacitance/ time delays.

  • Page 18: Configuration Pins

    UBX-G7020 - Hardware Integration Manual At initial start up in production, the UBX-G7020 will not have information about the supply voltage or oscillator settings required and hence may not be able to start up without this information. Hence an initial power-up requires starting in Safe Boot Mode in which the receiver runs from an internal ring oscillator.

  • Page 19: Communication Interfaces

    MAX3232. Hardware handshake signals and synchronous operation are not supported. A signal change on the UART RX pin can also be used to wake up the receiver in Power Save Mode (see u-blox 7 Receiver Description including Protocol Specification [3].).
  • Page 20 LEON-G100/G200-05S and above and on all LISA modules. The TX-ready feature is supported on version LEON FW 7.xx and LISA-U2 01S and above. For more information about DDC implementation refer to the u-blox 7 Receiver Description including Protocol Specification [3].

  • Page 21: Time Pulse

    2.2.6 SAFEBOOT_N Pin/ Safe Boot Mode PIO12 is the SAFEBOOT_N pin. If this pin is “low” at start up, the UBX-G7020 will start up in Safe Boot Mode and will not enter GPS/GNSS operation. In Safe Boot Mode the UBX-G7020 runs from an internal ring oscillator and starts regardless of any configuration provided by the configuration pins or configuration saved in SQI flash.

  • Page 22: Active Antenna Supervisor

    UBX-G7020 - Hardware Integration Manual 2.2.7 Active Antenna Supervisor u-blox 7 firmware supports active antenna supervisors. There is either a 2-pin or a 3-pin antenna supervisor. By default the 2-pin antenna supervisor is enabled. The antenna supervisor pins are located at PIO14, PIO15 and PIO16.
  • Page 23 T1 if a short circuit has been detected via U7 or if it’s not required (e.g. in Power Save Mode). The status of the active antenna can be checked by UBX-MON-HW message. See the u-blox 7 Receiver Description including Protocol Specification [3].

  • Page 24: System Reset

    2.3 System reset The UBX-G7020 provides a RESET_N pin to reset the system. The RESET_N is an edge triggered input only pin with an internal pull-up resistor. It is used to reset the system without affecting the temporary GNSS/GPS data saved in the backup memory.

  • Page 25: Clock Generation

    UBX-G7020 - Hardware Integration Manual 2.4 Clock generation The UBX-G7020 can be clocked either by a TCXO or by a crystal using the internal oscillator. The crystal oscillator option represents a low-cost solution where signal acquisition times are typically extended in case of weak signals.

  • Page 26: Crystal Or Tcxo Package Selection

    Temperature changes of the board, e.g. due to variation in power consumption of the UBX-G7020 or other adjacent components, may directly affect crystal/TCXO temperature. Through-hole mounted crystals are better isolated from these effects.

  • Page 27: Crystal Oscillator

    C14 and C15 shown in Figure 9. Each capacitor has an additional parasitic capacitance to GND in parallel formed by the circuit traces on the printed circuit board and the capacitance of the UBX-G7020 input- and output (XTAL_I and XTAL_O). The crystal oscillator will oscillate on its specified frequency only if the crystal “sees”...

  • Page 28: Tcxo

    UBX-G7020 - Hardware Integration Manual 1. Using a GPS/GNSS live signal: Observe the Clock Drift value inside the UBX-NAV-CLOCK message after the receiver has acquired a position. Its measurement unit is µs/s which is actually the same as ppm. 2. Using a 1-channel simulator: Observe the Doppler value inside the UBX-MON-PT message. The crystal offset in ppm can be calculated by dividing this value by -1575.42 Hz (observe the change in sign).
  • Page 29 UBX-G7020 - Hardware Integration Manual If a 1.8V VDD_IO supply is used in conjunction with a 1.8V TCXO, the TCXO must not be supplied by LDO_X_OUT. Instead the TCXO has to be supplied directly from VDD_IO, LDO_X_OUT is used to enable and disable the TCXO respectively.

  • Page 30: Real-Time Clock (Rtc)

    2.5 Real-Time Clock (RTC) The RTC section is located in the backup domain of the UBX-G7020. It is used to maintain time in the event of power failure at main supply, VDD_IO. The RTC is required for Hotstart, Warmstart, AssistNow Autonomous, AssistNow Offline and in some Power Save Mode operations.
  • Page 31 For Power Save Mode operations where the RTC is needed the time aiding cannot be used. Because the host does not have any information when the UBX-G7020 turns from OFF status to ON status during ON/OFF operation of Power Save Mode.

  • Page 32: Rf Front-End

    UBX-G7020 - Hardware Integration Manual 2.6 RF front-end The UBX-G7020 makes use of a RF subsystem, which can receive GPS and GLONASS frequencies. However, because of differing center frequencies the receiver has to be switched to GPS or GLONASS mode by using a UBX message.
  • Page 33 UBX-G7020 - Hardware Integration Manual Different design goals may be achieved through different implementations: 1. The primary focus is prevention of destruction of the receiver from large input signals. Here the GPS/GNSS performance under interference conditions is not important and suppression of the GPS/GNSS signal is permitted.

  • Page 34: Rf Front-End Circuit Options

    & directivity? 3. Are destructive RF power levels expected to reach the RF-input? Check against the maximum ratings provided in the UBX-G7020-Kx Data Sheet [1] and UBX-G7020-CT Data Sheet [2]! 4. Is interference from wireless transmitters expected? a. What are the characteristics of these signals (duty cycle, frequency range, power range, spectral purity)? b.
  • Page 35 UBX-G7020 - Hardware Integration Manual b. In the field: Is the antenna connector accessible by the user? The following subsections provide several options addressing the various questions above. In some applications, such as GSM transceivers, interference signals may exceed the maximum power rating of the LNA_IN input.
  • Page 36 2.6.2.3 Improved jamming immunity If the UBX-G7020 is exposed to an interference environment it is recommended to use additional filtering. Improved interference immunity with good GPS/GNSS performance is achieved when using a SAW/LNA/SAW configuration between the antenna and the UBX-G7020 matching network. The single-ended SAW Filter F2 (see section 3.6) can be placed in front of the LNA matching network to prevent saturation caused by very strong...
  • Page 37 Also, L3 should be selected to pass the DC fault current. The UBX-G7020 supports antenna supervision by adding external circuitry. For more information please see section 2.2.7. Make sure the DC block (C1) is in place; the UBX-G7020 LNA_IN has no internal DC block. Design-in GPS.G7-HW-10003...

  • Page 38: Usb

    UBX-G7020 - Hardware Integration Manual 2.7 USB The UBX-G7020 USB interface supports the full-speed data rate of 12 Mbit/s. It is compatible to USB 2.0 FS standard. The interface requires some external components in order to implement the physical characteristics required by the USB 2.0 specification.

  • Page 39: Jtag

    UBX-G7020 - Hardware Integration Manual 2.8 JTAG A JTAG interface can be used for testing and debugging. This interface allows failure analysis by the factory and boundary scan in production test. Function Remarks TDI / PIO13 Test Data Input Shared with PIO13...

  • Page 40: Layout

    2.9.2 Package footprint, copper and solder mask Copper and solder mask dimensioning recommendations for the UBX-G7020 packages are provided in this section. For all packages, the yellow color shows the copper (etch) dimensions, the green color shows the solder mask opening dimensions and the red circles indicate vias.
  • Page 41 The checkerboard pattern of the solder mask opening ensures even distribution of solder paste across the large center GND pad. Units below are in mm. Figure 22: QFN40 (UBX-G7020-Kx) recommended copper land pattern Figure 23: QFN40 (UBX-G7020-Kx) recommended solder mask opening pattern For mechanical specifications see UBX-G7020-Kx Data Sheet [1]. Design-in GPS.G7-HW-10003...
  • Page 42 UBX-G7020 - Hardware Integration Manual 2.9.2.2 WL-CSP50 Package Figure 24: QFN40 (UBX-G7020-CT) recommended copper land pattern Figure 25: QFN40 (UBX-G7020-CT) recommended solder mask opening pattern For mechanical specifications see UBX-G7020-CT Data Sheet [2]. Design-in GPS.G7-HW-10003 Objective Specification Page 42 of 74...

  • Page 43: System Configuration

    All the Low Level Configurations can be set in the eFuse inside the UBX-G7020 chip. If an SQI Flash is connected to the UBX-G7020 a partial Low Level Configuration, i.e. all except the VDD_IO POR threshold can be saved permanently in the SQI Flash.
  • Page 44 7 - GPS/GNSS Receiver Table 12: Low Level Configuration overview and default settings For detailed information about how to set the Low Level Configuration in SQI flash or eFuse see u-blox 7 Receiver description including protocol specification [3]. The VDD_IO threshold (POR_IO) which has to match the supply voltage of the SQI flash, must be always configured in eFuse;...
  • Page 45 With the Low Level Configuration set by the configuration pins, it should be able to start up with the correct clock/oscillator setting to enable the host to communicate with the UBX-G7020. Thus starting in Safe Boot Mode is not required and the host is able to communicate with the UBX-G7020 to set the eFuse Low Level Configuration.
  • Page 46 UBX-G7020 - Hardware Integration Manual 2.10.2.4 Low Level Configuration applying sequence Figure 26: Low level configuration applying sequence The Low Level Configuration can be checked with the UBX-MON-LLC message. Design-in GPS.G7-HW-10003 Objective Specification Page 46 of 74...

  • Page 47: Functional Configuration

    Figure 27: Functional Configuration Sequence 2.10.4 Functional configuration at run time Of course the Functional Configuration can be sent by the host at run time or can be fed to the UBX-G7020 at every start up, for example in a ROM based design.

  • Page 48: Component Selection

    UBX-G7020 - Hardware Integration Manual 3 Component Selection This section provides some information on components that are critical for the performance of the UBX-G7020 chip. Of course, temperature range specifications need only be as wide as required by a particular application.
  • Page 49 UBX-G7020 - Hardware Integration Manual Parameter Value duration, 3 cycles each plane Vibration 10 G RMS 30 Hz to 1500 Hz, duration of 6 hours Humidity 48 hours at 85 °C 85% relative humidity non-condensing Exposed at –40 °C for 30 minutes then to 85 °C for 30 minutes...

  • Page 50: Crystal (Y2)

    Table 16: Recommend parts list for GPS reference crystal A reference temperature can be defined with crystal supplier within this range. UBX-G7020-Kx Data Sheet [1] and UBX-G7020-CT Data Sheet [2]. Same reference temperature as in 2.2 Same reference temperature as in 2.2 Peak to peak deviation from the frequency versus AT temperature curve fit.

  • Page 51: Rtc Crystal (Y3)

    UBX-G7020 - Hardware Integration Manual Other crystals can be used provided they meet the specifications listed in Table 15. For reliable GPS performance particular attention must be paid to the temperature range and frequency slope specifications. 3.3 RTC crystal (Y3)

  • Page 52: External Lna Protection Filter (F2)

    UBX-G7020 - Hardware Integration Manual 3.6 External LNA protection filter (F2) Manufacturer Order No. System supported Comments TDK/ EPCOS B8401: B39162-B8401-P810 GPS+GLONASS High attenuation TDK/ EPCOS B3913: B39162B3913U410 GPS+GLONASS For automotive application TDK/ EPCOS B9850: B39162B9850P810 Low insertion loss TDK/ EPCOS...

  • Page 53: Lna_In Esd Protection Diode (D1)

    UBX-G7020 - Hardware Integration Manual 3.10 LNA_IN ESD protection diode (D1) Manufacturer Order No. ON Semiconductor ESD9R3.3ST5G Table 26: Recommend parts list for LNA_IN ESD protection diode 3.11 Operational amplifier (U6) Manufacturer Order No. Linear Technology LT6000 Linear Technology LT6003 Table 27: Recommend parts list for Operational Amplifier 3.12 Open-drain buffer (U4, U7 and U8)

  • Page 54: Inductor For Dcdc Converter (L2)

    UBX-G7020 - Hardware Integration Manual 3.15 Inductor for DCDC converter (L2) Parameter Value Self resonance frequency (SRF) > 30 MHz DC resistance (DCR) < 0.2 Ohm Rated current > 0.5 A Inductance 1.0…2.2 uH Table 32: DCDC inductor specifications It is recommended to use a shielded inductor.

  • Page 55: Standard Resistors

    UBX-G7020 - Hardware Integration Manual 3.17 Standard resistors Name Figure Type / Value USB data serial termination Figure 21 27R 5% 0.1W USB data serial termination Figure 21 27R 5% 0.1W Pull-down at VDD_USB Figure 21 1K 5% 0.1W Pull-up at antenna supervisor transistor Figure 7 100K 5% 0.1W...

  • Page 56: Design-In Checklists

    PCB and helps to achieve the best possible performance. Basically the checklist lists the recommendation from the previous sections. It is highly recommended to follow the Design-In Checklist when developing any u-blox 7 GPS/GNSS applications. This can significantly reduce development time and costs.

  • Page 57: Pin List

    UBX-G7020 - Hardware Integration Manual 4.1 Pin list Pin No Name Description Remarks MLF40 (WL- CSP50) 1 (E2) VDD_ANA Supply for analog part Has to be supplied by LDO_RF_OUT, pin 38 (F3). It is recommended to add some filtering, see Figure 5.

  • Page 58: Schematic And Bill Of Material Design-In Checklist

     Capacitor at LDO_X_OUT to GND has to be in place for crystal and TCXO designs: Section 2.4.  System power supply is capable of delivering maximum current as specified in the UBX-G7020-Kx Data Sheet [1] and UBX-G7020-CT Data Sheet [2].
  • Page 59 UBX-G7020 - Hardware Integration Manual  GPS/GNSS Crystal oscillator section is shielded by a GND guard ring: Section 2.9.1  RF signal lines are kept as short as possible and are designed as waveguides with proper impedance. Design-in Checklists GPS.G7-HW-10003...

  • Page 60: Production

    5.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the UBX-G7020-Kx Data Sheet [1] and UBX-G7020-CT Data Sheet [2]. 5.2 ESD handling precautions ESD prevention is based on establishing an Electrostatic Protective Area (EPA).

  • Page 61: Production

    For details on how to set the configuration see section 2.10. Programming the SQI flash can be accomplished using either u-center (the u-blox GPS/GNSS evaluation software) or via a firmware update utility. A flowchart detailing the sequence for applying the configuration and programming the SQI flash is shown below in section 5.4.1.

  • Page 62: Set The Low Level Configuration And Program The Optional Sqi Flash

    UBX-G7020 - Hardware Integration Manual 5.4.1 Set the Low Level Configuration and program the optional SQI flash Figure 28: Sequence in production to set the Low Level Configuration and program the optional SQI flash Production GPS.G7-HW-10003 Objective Specification Page 62 of 74...

  • Page 63: Test The Gps/Gnss Performance

    A standard in-circuit production test for the user application will use the UBX-MON-PT protocol message and will need access to a serial interface, e.g. DDC, SPI or UART. See the u-blox 7 Receiver Description including Protocol Specification [3] for the description of the UBX-MON-PT production test message. If PIO13 (EXTINT0 pin) is also accessible in production test, time aiding may be used in order to reduce test time.

  • Page 64: Appendix

    UBX-G7020 - Hardware Integration Manual Appendix A Reference schematics A.1 Cost optimized circuit Firmware runs out of ROM Passive antenna Crystal Single crystal feature used (RTC derived from main clock) UART and DDC for communication to host Figure 29: Cost optimized circuit Appendix GPS.G7-HW-10003...

  • Page 65: Best Performance Circuit

    UBX-G7020 - Hardware Integration Manual A.2 Best performance circuit 1.8V TCXO supplied by LDO_X_OUT External LNA RTC crystal Filtering for LNA supply UART and DDC interface Figure 30: Best performance circuit VDD_IO supply must be higher than 2.1V because of 1.8V TCXO used.

  • Page 66: Power Optimized Circuit

    UBX-G7020 - Hardware Integration Manual A.3 Power optimized circuit DCDC converter Crystal RTC crystal SPI interface No SQI flash Figure 31: Power optimized circuit Appendix GPS.G7-HW-10003 Objective Specification Page 66 of 74...

  • Page 67: Improved Jamming Immunity

    UBX-G7020 - Hardware Integration Manual A.4 Improved jamming immunity External SAW filter – LNA – SAW filter DCDC converter 1.8V TCXO supplied by LDO_X_OUT RTC crystal UART and DDC interface Figure 32: Standard circuit for an improved jamming immunity VDD_IO supply must be higher than 2.1V because of 1.8V TCXO used.

  • Page 68: 1.8V Design Using Tcxo

    UBX-G7020 - Hardware Integration Manual A.5 1.8V design using TCXO 1.8V TCXO UART and DDC interface RTC crystal UART and DDC interface External LNA Figure 33: Standard circuit using the SPI interface Appendix GPS.G7-HW-10003 Objective Specification Page 68 of 74...

  • Page 69: Circuit Using Active Antenna

    UBX-G7020 - Hardware Integration Manual A.6 Circuit using active antenna Active antenna 3V TCXO UART and DDC RTC crystal Figure 34: Standard circuit using active antenna VDD_IO supply must be higher than 3.2V because of 3V TCXO used. Appendix GPS.G7-HW-10003...

  • Page 70: Usb Self-Powered Circuit

    UBX-G7020 - Hardware Integration Manual A.7 USB self-powered circuit 1.8V TCXO External LNA SQI flash Figure 35: USB self-powered circuit VDD_IO supply must be higher than 2.1V because of 1.8V TCXO used. Appendix GPS.G7-HW-10003 Objective Specification Page 70 of 74...

  • Page 71: Usb Bus-Powered Circuit

    UBX-G7020 - Hardware Integration Manual A.8 USB bus-powered circuit 1.8V TCXO DCDC converter External LNA SQI flash Figure 36: USB bus-powered circuit Appendix GPS.G7-HW-10003 Objective Specification Page 71 of 74...

  • Page 72: Circuit Using 3-Pin Antenna Supervisor

    UBX-G7020 - Hardware Integration Manual A.9 Circuit using 3-pin antenna supervisor 3-pin antenna supervisor Crystal UART and DDC interface SQI flash Figure 37: Circuit using 3-pin antenna supervisor Appendix GPS.G7-HW-10003 Objective Specification Page 72 of 74...

  • Page 73: Related Documents

    UBX-G7020-Kx Data Sheet, Docu. No. GPS.G7-HW-12001 UBX-G7020-CT Data Sheet, Docu. No. GPS.G7-HW-12002 u-blox 7 Receiver description including protocol specification, Docu. No. GPS.G7-SW-12002 http://www.murata.com/products/emc/knowhow/index.html http://www.murata.com/products/emc/knowhow/pdf/4to5e.pdf For regular updates to u-blox documentation and to receive product change notifications please register on our homepage. Revision history Revision Date...

  • Page 74: Contact

    UBX-G7020 - Hardware Integration Manual Contact For complete contact information visit us at www.u-blox.com Headquarters u-blox AG Zuercherstrasse 68 CH-8800 Thalwil Switzerland Phone: +41 44 722 74 44 Fax: +41 44 722 74 47 E-mail: info@u-blox.com Offices North, Central and South America...

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