JVC CH-X470RF Service Manual page 28

CH-X470RF
TC9490FA (IC521) : DSP
1. Pin layout & Block diagram
2. Pin function (1/2)
No. Symbol
I/O
1 BCK O
2 LRCK O
3 AOUT O
4 DOUT O
5 IPF O
6 VDD3
7 VSS3
8 SBOK O
9 CLCK I/O
10 DATA O
11 SFSY O
12 SBSY O
13 /HSO O
14 /UHSO O
15 PVDD3
16 PDO O
17 TMAX O
18 LPFN
19 LPFO O
20 PVREF
21 VCOF O
22 AVSS3
23 SLCO O
24 RFI
25 AVSS3
1-28
48 47 46 45 44
DV 49
SS3
Clock
RO 50
generator
DV 51
DD3
LPF
DVR 52
1-bit
DAC
53
LO
DV 54
DD3
ZDET 55
V 56
SS5
57
BUS0
BUS1 58
59
BUS2
BUS3 60
Audio output
61
BUCK
circuit
Micro-
/CCE 62
controller
interface
/RST 63
V
64
DD5
1 2 3 4 5
Bit clock output pin.32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin. "L" for L channel and "H" for R channel.
Audio data output pin. MSB-first or LSB-first selected by command.
Digital data output pin. Outputs up to double-speed playback.
Correction flog output pin.
- Digital 3.3V power supply voltage pin.
- Digital GND pin.
Subcode Q data CRCC result output pin. "H" level when result is OK.
Sub-code P-W data read clock I/O pin. I/O polarity selectable by command.
Sub-code P-W data output pin.
Playback frames sync signal output pin.
Sub-code block sync output pin.
Playback speed mode flag output pin.
Playback speed mode flag output pin.
- PLL-only 3.3V power supply voltage pin.
EFM and PLCK phase difference signal output pin.
TMAX detection result output pin.
I Inverted input pin for PLL RF amp.
Output pin for PLL LPF amp.
- PLL-only VREF pin.
VCO filter pin.
- Analog GND pin.
DAC output pin for data slice level generation.
I RF signal input pin.
- Analog 3.3V power supply voltage pin.
43 42 41 40 39 38 37
PWM
Servo control
Digital equalizer
ROM
Address
automatic
circuit
RAM
adjustment circuit
CLV servo
16 k
RAM
Sync signal
protection
EFM
Digital output
Sub code
decoder
6 7 8 9 10 11 12
Function
36 35 34 33
32 TEZI
31
TEI
D/A
30 SBAD
29 FEI
A/D
28 RFRP
27
RFZI
26
RFCT
25 AV
DD3
24
RFI
Data
slicer
23 SLCO
22 AV
SS3
VCO
21 VCOF
20 PV
REF
19 LPFO
PLL
TMAX
18 LPFN
TMAX
17
13 14 15 16