Sharp ER-A770 Manual page 55

15. SRN
The SRN of the ER-A770 is compatible with the ER-A750.
16. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the ER-A770 cannot use the IRQ1 terminal
instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 8. Use the
channels 2, 3, 4, 5 and 6 for the ER-A7RS.
17. MCR
This paragraph describes MCR option (UP-E12MR) control defined
by ER-A770 hardware architecture.
2 channels of the serial port (interchangeable with 8251) built in the
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E12MR)
17-1. CPU interface
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the ER-A770 system is shown below.
Integrated as MPCA8
in the ER-A770 system.
CPU
MPCA7
RCVRDY1
INTMCR
ICI INTMCR
RCVRDY2
Signal description
RCP1 TRACK 1 CLOCK PULSE
RDD1 TRACK 1 DATA SIGNAL
RCP2 TRACK 2 CLOCK PULSE
RDD2 TRACK 2 DATA SIGNAL
CLS1 TRACK 1 CARD DETECTION SIGNAL
CLS2 TRACK 2 CARD DETECTION SIGNAL
RCVRDY1 TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2 TRACK 2 DATA RECEIVING SIGNAL
INTMCR INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
2 chip select signals for 8251 are generated inside MPCA8.
8251 x 2
RCP1
RCVCLK1 RCP1
RDD1
RCVDT1
RCP2
RCVCLK2
RDD2
RCVDT2
CLS1
/DSR1
CLS2
/DSR2 CLS2
RCVRDY1
RCVRDY2
CLS1,
CLS2
SYNC
17-2. MCR interface
The operating timing of the MCR interface signals is given below.
(1) Example of timing
CLS1/CLS2
RCP1/RCP2
RDD1/RDD2
(2) Detailed timing (relation between DATA and CLOCK PULSE)
RCP1/RCP2
RDD1/RDD2 "0"
Approx. 16µ s
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
18. 1-HOLE CLERK
On the ER-A770, 1-hole clerk key with up to 8 bits can be used.
The 1-hole clerk switch is controlled through the CKDC9 on the main
board.
ST0 ST3
CKDC9
"1" "1"
Min. 5µ s
/S2 /S9
LS138
X2
/CFSR