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SD-AT100H
IC3301 VHiTA1323F+-1: RF Signal Processor (TA1323F) (2/2)
Pin No.
Terminal Name
53
P1CI
54
P1BI
55
P1AI
56
GNDR
57
LDP2
58
P2AI
59
P2BI
60
P2CI
61
P2DI
62
GNDS
63
P2FP
64
P2Fn
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1FN
49
P1FP
50
LDP1
51
P1DI
52
P1CI
53
P1BI
54
P1AI
55
GNDR
56
LDP2
57
P2AI
58
P2BI
59
P2CI
60
P2DI
61
GNDS
62
P2FP
63
P2FN
64
1
Input/Output
Input
C input. (DVD)
Input
B input. (DVD)
Input
A input. (DVD)
—
GND terminal. (RF)
Input
APC polarity 2.
Input
A input. (CD)
Input
B input. (CD)
Input
C input. (CD)
Input
D input. (CD)
—
GND terminal. (Servo)
Input
FE+ input. (CD)
Input
FE– input. (CD)
APC1
sel-RF
R-gain
Adjust
sel-PD
F-gain
Adjust
F-gain
Adjust
sel-PD
sel-PD
T-gain
Adjust
APC2
2
3
4
5
6
Figure 106 BLOCK DIAGRAM OF IC
DC
EQ
FB
RF Ripple
creation
mode-IC
FEB
sel-FE
FE creation
DPDB
sel-TE
TEB
DPD-TE
creation
sel-DPD
mode-TE
3Beam-TE
creation
TEB
sel-LVL
VrA
Vref
7
8
9 10 11 12 13 14 15 16
– 106 –
Function
Output
Amp
FE-gain
Adjust
TE-gain
Adjust
Level
detect
Time
TCC1
constant
tcc1 (BUS)
adjustment
BUS
32
RFS
31
VccR
30
RFOp
RFOn
29
RPP
28
27
RPB
26
RPO
25
RPZ
NC
24
VccS
23
DFTN
22
FEO
21
TEO
20
LVL
19
VccP
18
VCKF
17
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