Bb Board - Sony VPL-PX20 Service Manual

3-2. BB Board

The BB board inputs the analog RGB signal from the QA board or digital RGB signal (TMSD:Panel
Link) from CN300, converts to the VESA60 equivalent XGA signals, superimposes the OSD signal, and
outputs to the BC board.
1. Scan Converter
PW * 64 (IC303) is used as the scan converter.
This IC incorporates the X86 base CPU core and frame memory SDRAM.
The 4 Mbits (512 KBytes) flash ROM (IC314) is equipped externally as the PROM and 1 Mbit (128
KBytes) SRAM (IC315) as the CPU RAM.
2. The External Data Bus
The external data bus is 16 bits. The CPU operates on 43.333 MHz which is obtained by dividing the
130 MHz memory clock by 3.
3. The External Flash RCM
The program of the external flash ROM can be rewritten by connecting a board for converting the
RS232C level to CN312. In this case, the EXTSW must be connected to GND to switch the
communication line, and the WDEN must be connected to GND to stop the operations of the watch
dog timer.
4. PW * * * * * 64
*
PW 64 normally operates as a sub CPU according to the commands from the main CPU on the Y
board. The commands are sent by asynchronous serial communication using TXD/RXD.
The OSD data itself is stored in IC314 which is the PW
the main CPU, the PW
To realize high-speed signal switching operations, the MUTE signal is directly sent to PW264.
The INTERLACE detection signal is directly sent from PW264 to Y.
5. PW264
Since PW264 is a X86 based CPU, the RESET signal must be input at a HIGH level.
For this reason, the open drain RESET signal of IC306 is reversed by the Schmidt inverter (IC317).
6. Memory Clock
The 130 MHz memory clock is obtained by multiplying the X300 21.667 MHz by six times.
The internal SDRAM operates on this frequency.
7. Internal Core
As the internal core operates on 2.5V, D3.3V is stepped down to 2.5V and supplied by IC312.
VPL-PX20/PX30
*
64 selects the contents displayed and superimposes.
*
64 memory. Based on the commands from
3-3