Theory Of Operation; Ba Board; Main Ic Functions; Signal Path - Sony VPL-PX20 Service Manual

3-1. BA Board

This circuit mainly performs the following processes.
a. VIDEO (C-VIDEO, Y/C, component), HDTV (Y PB PR) image processing
b. Sync separation processing

3-1-1. Main IC Functions

1. CXD2064 (IC221), digital comb filter
Performs NTSC3.58, PAL443 3-line applicable digital Y/C separation.
The operating clock (fsc) output from Pin 46 of CXA2123 (IC101) is input to Pin 37. The VIDEO
signal input from Pin 2 is digitally processed by this clock. The Y signal is then output from Pin 9
and the C signal from Pin 7.
2. CXA2123 (IC101), chroma decoder and sync processing
Chroma decoder/sync processing IC controlled by the I2C bus. It can process C-VIDEO signals and
Y/C signals. The C-VIDEO signal is input to Pin 1, the Y signal to Pin 44, and the C signal to Pin 43
to automatically differentiate between NTSC3.58, NTSC4.43, PAL, PAL-M, PAL-N, SECAM, and
B/W. When identified as NTSC3.58 or PAL, it supplies a clock to IC221 (CXD2084) to perform Y/C
separation. Y/C separation is performed in this IC when other systems are identified. The signals are
then converted to the Y/U/V signals, and the Y signal is output from Pin 21, the Cb signal from Pin
22, and the Cr signal from Pin 23.
In sync processing, the C-VIDEO/Y signal input is separated into H and V, and the H-sync signal is
output from Pin 9 while the V-sync signal is output from Pin 4. (For the 15 kHz COMPONENT and
RGB signals, only C.SYNC is input from Pin 19.)
3. CXA2101 (IC1601), HD interface
The HD interface is controlled by the I2C bus. It turns ON/OFF user-controlled COLOR, HUE,
SHARPNESS, and DYNAMIC PICTURE functions for signals input, performs detection axis
settings, and improves chroma transient, and converts signals to R, G, and B signals then outputs
them.
When the DTV (YpbPr, GBR) is input, the Y/Pb/Pr signal G/B/R are input to Pins 11, 10, and 9
respectively. COMPONENT is input to Pin 5 (Y), 4 (Cb), and 3 (Cr). The Video signal is decoded by
IC101, and then input to Pins 69 (Y), 68 (Cb), and 67 (Cr).
They are then subject to various controls, converted to R, G, and B signals, and output from Pins 35
(R), 37 (G), and 39 (B).

3-1-2. Signal Path

1. Path of VIDEO signal
The VIDEO and Y/C signals input from CN102 are input to Pins 1, 44, and 43 of IC101 via buffers
Q107 (composite video), Q109 (Y), and Q101 (C).
For PAL and NTSC3.58, the signal amplified by two times by IC101 is output from Pin 3, passed
through the low pass filter composed of Q120, L111, L110, C211, C210, and C143, input to Pin 2 of
IC221 (comb filter), Y/C separated, output from Pins 9, Y, 7, and C, passed through the low pass
filter composed of L112, C215, L113, and C219, after which the Y signal is input to Pin 5 of IC101
and the C signal is input to Pin 7. All other signals are processed in IC101, converted to the Y, U, and
V signals, and output from Pins 21 (Y), 22 (B-Y), and 23 (R-Y). They are then input to Pins 69, 68,
and 67 of IC102 for the above processing by CXA2101, and output.
VPL-PX20/PX30
Section 3

Theory of Operation

3-1