Path Of Sync Processing; Clamp Pulse Generation Circuit - Sony VPL-PX20 Service Manual

2. Path of component (Y/R-Y/B-Y) signal, 15kRGB signal
The component video signal input from CN101 is passed through the buffer Q116/ Q115/Q117, and
input to Pins 5 (Y), 4 (Cb), and 3 (Cr). The 15kRGB signal is passed through the same path as the
component signal, input to Pins 5 (G), 4 (B), and 3 (R) of IC102 for the above processing by
CXA2101, and output.
3. Path of HDTV (Y, PB, PR) signal
The Y/Pb/Pr video signal input from CN101 is input to Pins 11 (Y), 10 (Pb), and 9 (Pr) of IC102 via
the buffer Q116/115/117 for the above processing by CXA2101, and output.

3-1-3. Path of SYNC Processing

1. When the VIDEO signal is selected
The signal input to IC101 is sync separated internally, and the H and V SYNC from Pins 9 and 4 are
output.
The equivalent pulse of the signal output from Pin 9 is eliminated as it is imposed with PLL. After
this, it is input to Pins 65 and 66 of IC102, selected, and output from Pins 29 and 28. The H sync
output is reversed by IC259, input to IC256, noise-eliminated, output from Pin 7, waveform-rectified
by IC257, and output from CN101.
2. For component signal (15K) and 15kRGB signals
The C SYNC signal rectified by the QA board is input to Pin 19 of IC101. The signal output from
Pins 9 and 4 are input to Pin 2 of IC1021. The rest is the same process as for Video signals.
3. When HDTV (YPbPr, GBR), components signals other than 15K are input
The signal input from CN101 is input to Pins 11, 7, and 8 of IC102 in the order of Y/G, H, and V.
IC102 automatically determines if the signal is SonG, C.SYNC, or HV separate, and outputs the
signal from Pins 29 and 28. The rest is the same process as for Video signals.

3-1-4. Clamp Pulse Generation Circuit

1. Path of VIDEO, component (Y/R-Y/B-Y) signal, and 15 kRGB signal
The SGP output from Pin 10 of IC101 is waveform-rectified by IC263, input to IC251, subject to
selection with the HDTV signal input, output from Pin 1, reversed by IC252, and output from
CN101.
2. When HDTV (YPbPr, GBR), component signals other than 15K are input
The H.sync output from Pin 29 of IC102 is reversed by IC259, and then input to IC256.
Clamp pulses are generated by this IC, output from Pin 5, waveform-rectified by IC259 and IC257,
input to IC251, selected, and output from CN101.
3-2
VPL-PX20/PX30