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2-1-6 MIC3 (KM681000C ; CMOS 1M SRAM)
TOP VIEW
N.C
1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
VSS
16
BLOCK DIAGRAM
Clk gen.
A4
A5
A6
A7
Row
A8
select
A12
A13
A14
A15
A16
Data
I/O
1
cont
I/O
8
Data
cont
CS1
Control
CS2
logic
WE
OE
VCC
32
A15
31
CS2
30
WE
29
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
CS1
22
21
I/O8
I/O7
20
19
I/O6
18
I/O5
17
I/O4
Precharge circuit.
Memory array
1024 rows
128· 8 columns
I/O Circuit
Column select
A0
A1 A2
A3 A9
A10
Name
Function
CS
,CS
Chip Select Inputs
1
2
OE
Output Enable
WE
Write Enable
A
~A
Address Inputs
0
16
Reference Information
V
CC
V
SS
A11
Name
Function
I/O
~I/O
Data Inputs/Out-
1
8
Vcc
Power
Vss
Ground
N.C
No Connection
2-9
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